periphery: convert periphery bundle traits to work with system-level multi-io module
This commit is contained in:
@ -3,18 +3,14 @@ package sifive.blocks.devices.spi
|
||||
|
||||
import Chisel._
|
||||
import config.Field
|
||||
import diplomacy.LazyModule
|
||||
import rocketchip.{
|
||||
HasTopLevelNetworks,
|
||||
HasTopLevelNetworksBundle,
|
||||
HasTopLevelNetworksModule
|
||||
}
|
||||
import uncore.tilelink2.{TLFragmenter, TLWidthWidget}
|
||||
import diplomacy.{LazyModule,LazyMultiIOModuleImp}
|
||||
import rocketchip.HasSystemNetworks
|
||||
import uncore.tilelink2.{TLFragmenter,TLWidthWidget}
|
||||
import util.HeterogeneousBag
|
||||
|
||||
case object PeripherySPIKey extends Field[Seq[SPIParams]]
|
||||
|
||||
trait HasPeripherySPI extends HasTopLevelNetworks {
|
||||
trait HasPeripherySPI extends HasSystemNetworks {
|
||||
val spiParams = p(PeripherySPIKey)
|
||||
val spis = spiParams map { params =>
|
||||
val spi = LazyModule(new TLSPI(peripheryBusBytes, params))
|
||||
@ -24,22 +20,28 @@ trait HasPeripherySPI extends HasTopLevelNetworks {
|
||||
}
|
||||
}
|
||||
|
||||
trait HasPeripherySPIBundle extends HasTopLevelNetworksBundle {
|
||||
val outer: HasPeripherySPI
|
||||
val spis = HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_)))
|
||||
trait HasPeripherySPIBundle {
|
||||
val spis: HeterogeneousBag[SPIPortIO]
|
||||
|
||||
def SPItoGPIOPins(dummy: Int = 1): Seq[SPIGPIOPort] = spis.map { s =>
|
||||
val pin = Module(new SPIGPIOPort(s.c))
|
||||
pin.io.spi <> s
|
||||
pin
|
||||
}
|
||||
}
|
||||
|
||||
trait HasPeripherySPIModule extends HasTopLevelNetworksModule {
|
||||
trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIBundle {
|
||||
val outer: HasPeripherySPI
|
||||
val io: HasPeripherySPIBundle
|
||||
(io.spis zip outer.spis).foreach { case (io, device) =>
|
||||
val spis = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
|
||||
|
||||
(spis zip outer.spis).foreach { case (io, device) =>
|
||||
io <> device.module.io.port
|
||||
}
|
||||
}
|
||||
|
||||
case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
|
||||
|
||||
trait HasPeripherySPIFlash extends HasTopLevelNetworks {
|
||||
trait HasPeripherySPIFlash extends HasSystemNetworks {
|
||||
val spiFlashParams = p(PeripherySPIFlashKey)
|
||||
val qspi = spiFlashParams map { params =>
|
||||
val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params))
|
||||
@ -50,16 +52,15 @@ trait HasPeripherySPIFlash extends HasTopLevelNetworks {
|
||||
}
|
||||
}
|
||||
|
||||
trait HasPeripherySPIFlashBundle extends HasTopLevelNetworksBundle {
|
||||
val outer: HasPeripherySPIFlash
|
||||
val qspi = HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_)))
|
||||
trait HasPeripherySPIFlashBundle {
|
||||
val qspi: HeterogeneousBag[SPIPortIO]
|
||||
}
|
||||
|
||||
trait HasPeripherySPIFlashModule extends HasTopLevelNetworksModule {
|
||||
trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIFlashBundle {
|
||||
val outer: HasPeripherySPIFlash
|
||||
val io: HasPeripherySPIFlashBundle
|
||||
val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))))
|
||||
|
||||
(io.qspi zip outer.qspi) foreach { case (io, device) =>
|
||||
(qspi zip outer.qspi) foreach { case (io, device) =>
|
||||
io <> device.module.io.port
|
||||
}
|
||||
}
|
||||
|
Reference in New Issue
Block a user