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periphery: convert periphery bundle traits to work with system-level multi-io module

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This commit is contained in:
Henry Cook
2017-06-05 14:33:53 -07:00
parent 79f64de12c
commit d4bb8a77ea
8 changed files with 122 additions and 117 deletions
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33
src/main/scala/devices/pwm/PWMPeriphery.scala
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@@ -3,27 +3,23 @@ package sifive.blocks.devices.pwm
import Chisel._
import config.Field
import diplomacy.LazyModule
import rocketchip.{
HasTopLevelNetworks,
HasTopLevelNetworksBundle,
HasTopLevelNetworksModule
}
import diplomacy.{LazyModule,LazyMultiIOModuleImp}
import rocketchip.HasSystemNetworks
import uncore.tilelink2.TLFragmenter
import util.HeterogeneousBag
import sifive.blocks.devices.gpio._
class PWMPortIO(c: PWMParams) extends Bundle {
class PWMPortIO(val c: PWMParams) extends Bundle {
val port = Vec(c.ncmp, Bool()).asOutput
override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
}
class PWMPinsIO(c: PWMParams) extends Bundle {
class PWMPinsIO(val c: PWMParams) extends Bundle {
val pwm = Vec(c.ncmp, new GPIOPin)
}
class PWMGPIOPort(c: PWMParams) extends Module {
class PWMGPIOPort(val c: PWMParams) extends Module {
val io = new Bundle {
val pwm = new PWMPortIO(c).flip()
val pins = new PWMPinsIO(c)
@@ -34,7 +30,7 @@ class PWMGPIOPort(c: PWMParams) extends Module {
case object PeripheryPWMKey extends Field[Seq[PWMParams]]
trait HasPeripheryPWM extends HasTopLevelNetworks {
trait HasPeripheryPWM extends HasSystemNetworks {
val pwmParams = p(PeripheryPWMKey)
val pwms = pwmParams map { params =>
val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
@@ -44,16 +40,21 @@ trait HasPeripheryPWM extends HasTopLevelNetworks {
}
}
trait HasPeripheryPWMBundle extends HasTopLevelNetworksBundle {
val outer: HasPeripheryPWM
val pwms = HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_)))
trait HasPeripheryPWMBundle {
val pwms: HeterogeneousBag[PWMPortIO]
def PWMtoGPIOPins(dummy: Int = 1): Seq[PWMGPIOPort] = pwms.map { p =>
val pin = Module(new PWMGPIOPort(p.c))
pin.io.pwm <> p
pin
}
}
trait HasPeripheryPWMModule extends HasTopLevelNetworksModule {
trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
val outer: HasPeripheryPWM
val io: HasPeripheryPWMBundle
val pwms = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
(io.pwms zip outer.pwms) foreach { case (io, device) =>
(pwms zip outer.pwms) foreach { case (io, device) =>
io.port := device.module.io.gpio
}
}