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periphery: convert periphery bundle traits to work with system-level multi-io module

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This commit is contained in:
Henry Cook
2017-06-05 14:33:53 -07:00
parent 79f64de12c
commit d4bb8a77ea
8 changed files with 122 additions and 117 deletions
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27
src/main/scala/devices/mockaon/MockAONPeriphery.scala
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@ -3,20 +3,14 @@ package sifive.blocks.devices.mockaon
import Chisel._
import config.Field
import coreplex.CoreplexRISCVPlatform
import diplomacy.LazyModule
import rocketchip.{
HasTopLevelNetworks,
HasTopLevelNetworksBundle,
HasTopLevelNetworksModule
}
import diplomacy.{LazyModule, LazyMultiIOModuleImp}
import rocketchip.{HasSystemNetworks, HasCoreplexRISCVPlatform}
import uncore.tilelink2.{IntXing, TLAsyncCrossingSource, TLFragmenter}
import util.ResetCatchAndSync
case object PeripheryMockAONKey extends Field[MockAONParams]
trait HasPeripheryMockAON extends HasTopLevelNetworks {
val coreplex: CoreplexRISCVPlatform
trait HasPeripheryMockAON extends HasSystemNetworks with HasCoreplexRISCVPlatform {
// We override the clock & Reset here so that all synchronizers, etc
// are in the proper clock domain.
val mockAONParams= p(PeripheryMockAONKey)
@ -27,15 +21,18 @@ trait HasPeripheryMockAON extends HasTopLevelNetworks {
intBus.intnode := aon_int.intnode
}
trait HasPeripheryMockAONBundle extends HasTopLevelNetworksBundle {
val aon = new MockAONWrapperBundle()
trait HasPeripheryMockAONBundle {
val aon: MockAONWrapperBundle
def coreResetCatchAndSync(core_clock: Clock) = {
ResetCatchAndSync(core_clock, aon.rsts.corerst, 20)
}
}
trait HasPeripheryMockAONModule extends HasTopLevelNetworksModule {
trait HasPeripheryMockAONModuleImp extends LazyMultiIOModuleImp with HasPeripheryMockAONBundle {
val outer: HasPeripheryMockAON
val io: HasPeripheryMockAONBundle
val aon = IO(new MockAONWrapperBundle)
io.aon <> outer.aon.module.io
aon <> outer.aon.module.io
// Explicit clock & reset are unused in MockAONWrapper.
// Tie to check this assumption.