riscv/sifive-blocks
1
0
Fork 0
Code Releases Activity

PMU: adapt to new chisel API (#45)

Browse Source
This commit is contained in:
Wesley W. Terpstra 2017-11-02 15:44:02 -07:00 committed by GitHub
parent 90e6ea1d2d
commit d1d2f47f60
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/devices/mockaon/PMU.scala
View File

@ -131,7 +131,9 @@ class PMU(val c: PMUConfig) extends Module {
val resetCauses = new ResetCauses().asInput val resetCauses = new ResetCauses().asInput
} }
val core = Module(new PMUCore(c)(resetIn = Reg(next = Reg(next = reset)))) val coreReset = Reg(next = Reg(next = reset))
val core = Module(new PMUCore(c)(resetIn = coreReset))
io <> core.io io <> core.io
core.io.wakeup.reset := false // this is implied by resetting the PMU core.io.wakeup.reset := false // this is implied by resetting the PMU