riscv/sifive-blocks
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TLSPI: address parameter must now be a sequence.

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This commit is contained in:
Megan Wachs 2017-03-21 17:51:28 -07:00
parent 77246eaada
commit c6d7326669
1 changed files with 1 additions and 1 deletions
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src/main/scala/devices/spi/TLSPI.scala
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@ -110,7 +110,7 @@ class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLS
abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule {
require(isPow2(c.rSize))
val device = new SimpleDevice("spi", Seq("sifive,spi0"))
val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), device = device, beatBytes = w)
val rnode = TLRegisterNode(address = Seq(AddressSet(c.rAddress, c.rSize-1)), device = device, beatBytes = w)
val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
}