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mig: track change to Blind port API in rocket

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This commit is contained in:
Wesley W. Terpstra 2017-01-19 19:53:03 -08:00
parent 45c491cd69
commit c68e44ec55
1 changed files with 2 additions and 2 deletions
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src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
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@ -27,7 +27,7 @@ class XilinxVC707MIGIO extends Bundle with VC707MIGUnidirectionalIODDR
class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters { class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters {
val node = TLInputNode() val node = TLInputNode()
val axi4 = AXI4InternalOutputNode(AXI4SlavePortParameters( val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters( slaves = Seq(AXI4SlaveParameters(
address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)), address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
regionType = RegionType.UNCACHED, regionType = RegionType.UNCACHED,
@ -35,7 +35,7 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
supportsWrite = TransferSizes(1, 256*8), supportsWrite = TransferSizes(1, 256*8),
supportsRead = TransferSizes(1, 256*8), supportsRead = TransferSizes(1, 256*8),
interleavedId = Some(0))), interleavedId = Some(0))),
beatBytes = 8)) beatBytes = 8)))
val xing = LazyModule(new TLAsyncCrossing) val xing = LazyModule(new TLAsyncCrossing)
val toaxi4 = LazyModule(new TLToAXI4(idBits = 4)) val toaxi4 = LazyModule(new TLToAXI4(idBits = 4))