riscv/sifive-blocks
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vc707mig: use an external ibuf

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This makes it possible to also drive a PLL of our own from the crystal.
This commit is contained in:
Wesley W. Terpstra
2017-05-12 23:07:10 -07:00
parent 0ed21ba465
commit c4c158963c
2 changed files with 4 additions and 6 deletions
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5
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
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@@ -77,9 +77,8 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
io.port.ddr3_odt := blackbox.io.ddr3_odt io.port.ddr3_odt := blackbox.io.ddr3_odt
//inputs //inputs
//differential system clock //NO_BUFFER clock
blackbox.io.sys_clk_n := io.port.sys_clk_n blackbox.io.sys_clk_i := io.port.sys_clk_i
blackbox.io.sys_clk_p := io.port.sys_clk_p
//user interface signals //user interface signals
val axi_async = axi4.bundleIn(0) val axi_async = axi4.bundleIn(0)

5
src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
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@@ -31,9 +31,8 @@ trait VC707MIGIODDR extends Bundle {
//reused directly in io bundle for sifive.blocks.devices.xilinxvc707mig //reused directly in io bundle for sifive.blocks.devices.xilinxvc707mig
trait VC707MIGIOClocksReset extends Bundle { trait VC707MIGIOClocksReset extends Bundle {
//inputs //inputs
//differential system clocks //"NO_BUFFER" clock source (must be connected to IBUF outside of IP)
val sys_clk_n = Bool(INPUT) val sys_clk_i = Bool(INPUT)
val sys_clk_p = Bool(INPUT)
//user interface signals //user interface signals
val ui_clk = Clock(OUTPUT) val ui_clk = Clock(OUTPUT)
val ui_clk_sync_rst = Bool(OUTPUT) val ui_clk_sync_rst = Bool(OUTPUT)