xilinx mig: put a buffer infront of the controller (#13)
This makes placement of the L2 and DDR controller easier.
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@ -36,10 +36,12 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
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val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
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val deint = LazyModule(new AXI4Deinterleaver(p(coreplex.CacheBlockBytes)))
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val yank = LazyModule(new AXI4UserYanker)
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val buffer = LazyModule(new AXI4Buffer)
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xing.node := node
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val monitor = (toaxi4.node := xing.node)
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axi4 := yank.node
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axi4 := buffer.node
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buffer.node := yank.node
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yank.node := deint.node
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deint.node := indexer.node
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indexer.node := toaxi4.node
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@ -85,7 +87,7 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
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xing.module.io.in_reset := reset
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xing.module.io.out_clock := blackbox.io.ui_clk
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xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
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(Seq(toaxi4, indexer, deint, yank) ++ monitor) foreach { lm =>
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(Seq(toaxi4, indexer, deint, yank, buffer) ++ monitor) foreach { lm =>
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lm.module.clock := blackbox.io.ui_clk
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lm.module.reset := blackbox.io.ui_clk_sync_rst
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}
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