spi: include mem region (#23)
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@ -109,15 +109,7 @@ class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLS
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abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule {
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require(isPow2(c.rSize))
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val device = new SimpleDevice("spi", Seq("sifive,spi0")) {
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override def describe(resources: ResourceBindings): Description = {
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val Description(name, mapping) = super.describe(resources)
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val rangesSeq = resources("ranges").map(_.value)
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val ranges = if (rangesSeq.isEmpty) Map() else Map("ranges" -> rangesSeq)
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Description(name, mapping ++ ranges)
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}
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}
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val device = new SimpleDevice("spi", Seq("sifive,spi0"))
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val rnode = TLRegisterNode(address = Seq(AddressSet(c.rAddress, c.rSize-1)), device = device, beatBytes = w)
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val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
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}
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@ -95,7 +95,7 @@ abstract class TLSPIFlashBase(w: Int, c: SPIFlashParamsBase)(implicit p: Paramet
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require(isPow2(c.fSize))
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val fnode = TLManagerNode(1, TLManagerParameters(
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address = Seq(AddressSet(c.fAddress, c.fSize-1)),
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resources = Seq(Resource(device, "ranges")),
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resources = device.reg("mem"),
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regionType = RegionType.UNCACHED,
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executable = true,
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supportsGet = TransferSizes(1, 1),
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