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spi: include mem region (#23)

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This commit is contained in:
Wesley W. Terpstra
2017-06-28 17:46:45 -07:00
committed by GitHub
parent 3d8c502fce
commit a8e20f447c
2 changed files with 2 additions and 10 deletions
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10
src/main/scala/devices/spi/TLSPI.scala
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@@ -109,15 +109,7 @@ class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLS
abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule {
require(isPow2(c.rSize))
val device = new SimpleDevice("spi", Seq("sifive,spi0")) {
override def describe(resources: ResourceBindings): Description = {
val Description(name, mapping) = super.describe(resources)
val rangesSeq = resources("ranges").map(_.value)
val ranges = if (rangesSeq.isEmpty) Map() else Map("ranges" -> rangesSeq)
Description(name, mapping ++ ranges)
}
}
val device = new SimpleDevice("spi", Seq("sifive,spi0"))
val rnode = TLRegisterNode(address = Seq(AddressSet(c.rAddress, c.rSize-1)), device = device, beatBytes = w)
val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
}

2
src/main/scala/devices/spi/TLSPIFlash.scala
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@@ -95,7 +95,7 @@ abstract class TLSPIFlashBase(w: Int, c: SPIFlashParamsBase)(implicit p: Paramet
require(isPow2(c.fSize))
val fnode = TLManagerNode(1, TLManagerParameters(
address = Seq(AddressSet(c.fAddress, c.fSize-1)),
resources = Seq(Resource(device, "ranges")),
resources = device.reg("mem"),
regionType = RegionType.UNCACHED,
executable = true,
supportsGet = TransferSizes(1, 1),