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spi: put a request buffer infront of SPI

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This will prevent SPI from blocking other pbus requests.
This commit is contained in:
Wesley W. Terpstra
2017-08-19 12:36:28 -07:00
parent f266b55da9
commit a814cba04f
1 changed files with 6 additions and 3 deletions
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9
src/main/scala/devices/spi/SPIPeriphery.scala
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@@ -4,8 +4,8 @@ package sifive.blocks.devices.spi
import Chisel._
import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
import freechips.rocketchip.tilelink.{TLFragmenter}
import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp,BufferParams}
import freechips.rocketchip.tilelink.{TLFragmenter,TLBuffer}
import freechips.rocketchip.util.HeterogeneousBag
case object PeripherySPIKey extends Field[Seq[SPIParams]]
@@ -41,7 +41,10 @@ trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
val qspis = spiFlashParams map { params =>
val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
qspi.rnode := pbus.toVariableWidthSlaves
qspi.fnode := TLFragmenter(1, pbus.blockBytes)(pbus.toFixedWidthSlaves)
qspi.fnode :=
TLFragmenter(1, pbus.blockBytes)(
TLBuffer(BufferParams(8), BufferParams.none)(
pbus.toFixedWidthSlaves))
ibus.fromSync := qspi.intnode
qspi
}