From a814cba04ffc83b0715339ee650eac358d7852b8 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sat, 19 Aug 2017 12:36:28 -0700 Subject: [PATCH] spi: put a request buffer infront of SPI This will prevent SPI from blocking other pbus requests. --- src/main/scala/devices/spi/SPIPeriphery.scala | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala index 8097894..6e58647 100644 --- a/src/main/scala/devices/spi/SPIPeriphery.scala +++ b/src/main/scala/devices/spi/SPIPeriphery.scala @@ -4,8 +4,8 @@ package sifive.blocks.devices.spi import Chisel._ import freechips.rocketchip.config.Field import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus} -import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp} -import freechips.rocketchip.tilelink.{TLFragmenter} +import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp,BufferParams} +import freechips.rocketchip.tilelink.{TLFragmenter,TLBuffer} import freechips.rocketchip.util.HeterogeneousBag case object PeripherySPIKey extends Field[Seq[SPIParams]] @@ -41,7 +41,10 @@ trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus { val qspis = spiFlashParams map { params => val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params)) qspi.rnode := pbus.toVariableWidthSlaves - qspi.fnode := TLFragmenter(1, pbus.blockBytes)(pbus.toFixedWidthSlaves) + qspi.fnode := + TLFragmenter(1, pbus.blockBytes)( + TLBuffer(BufferParams(8), BufferParams.none)( + pbus.toFixedWidthSlaves)) ibus.fromSync := qspi.intnode qspi }