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Merge pull request #14 from sifive/async-pcie

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Async PCIe
This commit is contained in:
Wesley W. Terpstra 2017-05-12 23:15:14 -07:00 committed by GitHub
commit 9c8fe44670
4 changed files with 24 additions and 17 deletions
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5
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
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@ -77,9 +77,8 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
io.port.ddr3_odt := blackbox.io.ddr3_odt
//inputs
//differential system clock
blackbox.io.sys_clk_n := io.port.sys_clk_n
blackbox.io.sys_clk_p := io.port.sys_clk_p
//NO_BUFFER clock
blackbox.io.sys_clk_i := io.port.sys_clk_i
//user interface signals
val axi_async = axi4.bundleIn(0)

15
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
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@ -20,9 +20,9 @@ class XilinxVC707PCIeX1IO extends Bundle with VC707AXIToPCIeX1IOSerial
}
class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
val slave = TLInputNode()
val control = TLInputNode()
val master = TLOutputNode()
val slave = TLAsyncInputNode()
val control = TLAsyncInputNode()
val master = TLAsyncOutputNode()
val intnode = IntOutputNode()
val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
@ -33,21 +33,24 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
AXI4Deinterleaver(p(coreplex.CacheBlockBytes))(
AXI4IdIndexer(idBits=4)(
TLToAXI4(beatBytes=8)(
slave)))))
TLAsyncCrossingSink()(
slave))))))
axi_to_pcie_x1.control :=
AXI4Buffer()(
AXI4UserYanker()(
TLToAXI4(beatBytes=4)(
TLFragmenter(4, p(coreplex.CacheBlockBytes))(
control))))
TLAsyncCrossingSink()(
control)))))
master :=
TLAsyncCrossingSource()(
TLWidthWidget(8)(
AXI4ToTL()(
AXI4UserYanker(capMaxFlight=Some(8))(
AXI4Fragmenter()(
axi_to_pcie_x1.master))))
axi_to_pcie_x1.master)))))
intnode := axi_to_pcie_x1.intnode

16
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
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@ -8,15 +8,18 @@ import rocketchip.{
HasTopLevelNetworksModule,
HasTopLevelNetworksBundle
}
import uncore.tilelink2.TLWidthWidget
import uncore.tilelink2._
trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
fsb.node := xilinxvc707pcie.master
xilinxvc707pcie.slave := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
intBus.intnode := xilinxvc707pcie.intnode
private val intXing = LazyModule(new IntXing)
fsb.node := TLAsyncCrossingSink()(xilinxvc707pcie.master)
xilinxvc707pcie.slave := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
xilinxvc707pcie.control := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
intBus.intnode := intXing.intnode
intXing.intnode := xilinxvc707pcie.intnode
}
trait HasPeripheryXilinxVC707PCIeX1Bundle extends HasTopLevelNetworksBundle {
@ -28,4 +31,7 @@ trait HasPeripheryXilinxVC707PCIeX1Module extends HasTopLevelNetworksModule {
val io: HasPeripheryXilinxVC707PCIeX1Bundle
io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
outer.xilinxvc707pcie.module.clock := outer.xilinxvc707pcie.module.io.port.axi_aclk_out
outer.xilinxvc707pcie.module.reset := ~io.xilinxvc707pcie.axi_aresetn
}

5
src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
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@ -31,9 +31,8 @@ trait VC707MIGIODDR extends Bundle {
//reused directly in io bundle for sifive.blocks.devices.xilinxvc707mig
trait VC707MIGIOClocksReset extends Bundle {
//inputs
//differential system clocks
val sys_clk_n = Bool(INPUT)
val sys_clk_p = Bool(INPUT)
//"NO_BUFFER" clock source (must be connected to IBUF outside of IP)
val sys_clk_i = Bool(INPUT)
//user interface signals
val ui_clk = Clock(OUTPUT)
val ui_clk_sync_rst = Bool(OUTPUT)