periphery: peripherals now in coreplex (#26)
* periphery: peripherals now in coreplex * use fromAsyncFIFOMaster
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@ -2,8 +2,8 @@
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package sifive.blocks.devices.uart
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import Chisel._
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import freechips.rocketchip.chip.RTCPeriod
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.coreplex.RTCPeriod
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import freechips.rocketchip.diplomacy.DTSTimebase
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.tilelink._
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@ -205,7 +205,7 @@ trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg
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val rxm = Module(new UARTRx(params))
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val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
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val divinit = p(DTSTimebase) * p(RTCPeriod) / 115200
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val divinit = p(DTSTimebase) * BigInt(p(RTCPeriod).getOrElse(1)) / 115200
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val div = Reg(init = UInt(divinit, uartDivisorBits))
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private val stopCountBits = log2Up(uartStopBits)
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