riscv/sifive-blocks
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shiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate

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This commit is contained in:
Megan Wachs 2017-09-06 10:59:07 -07:00
parent 4381e395af
commit 97c3fcb4b6
3 changed files with 6 additions and 6 deletions
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6
src/main/scala/devices/i2c/I2CPins.scala
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@ -3,7 +3,7 @@ package sifive.blocks.devices.i2c
import Chisel._ import Chisel._
import chisel3.experimental.{withClockAndReset} import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.util.SynchronizerShiftRegInit import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
import sifive.blocks.devices.pinctrl.{Pin, PinCtrl} import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
class I2CPins[T <: Pin](pingen: () => T) extends Bundle { class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
@ -18,12 +18,12 @@ class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
withClockAndReset(clock, reset) { withClockAndReset(clock, reset) {
scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B) scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
scl.o.oe := i2c.scl.oe scl.o.oe := i2c.scl.oe
i2c.scl.in := SynchronizerShiftRegInit(scl.i.ival, syncStages, init = Bool(true), i2c.scl.in := SyncResetSynchronizerShiftReg(scl.i.ival, syncStages, init = Bool(true),
name = Some("i2c_scl_sync")) name = Some("i2c_scl_sync"))
sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B) sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
sda.o.oe := i2c.sda.oe sda.o.oe := i2c.sda.oe
i2c.sda.in := SynchronizerShiftRegInit(sda.i.ival, syncStages, init = Bool(true), i2c.sda.in := SyncResetSynchronizerShiftReg(sda.i.ival, syncStages, init = Bool(true),
name = Some("i2c_sda_sync")) name = Some("i2c_sda_sync"))
} }
} }

2
src/main/scala/devices/spi/SPIPhysical.scala
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@ -2,7 +2,7 @@
package sifive.blocks.devices.spi package sifive.blocks.devices.spi
import Chisel._ import Chisel._
import freechipchips.rocketchip.util.ShiftRegInit import freechips.rocketchip.util.ShiftRegInit
class SPIMicroOp(c: SPIParamsBase) extends SPIBundle(c) { class SPIMicroOp(c: SPIParamsBase) extends SPIBundle(c) {
val fn = Bits(width = 1) val fn = Bits(width = 1)

4
src/main/scala/devices/uart/UARTPeriphery.scala
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@ -4,7 +4,7 @@ package sifive.blocks.devices.uart
import Chisel._ import Chisel._
import chisel3.experimental.{withClockAndReset} import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field import freechips.rocketchip.config.Field
import freechips.rocketchip.util.SynchronizerShiftRegInit import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus} import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import sifive.blocks.devices.pinctrl.{Pin} import sifive.blocks.devices.pinctrl.{Pin}
@ -51,7 +51,7 @@ class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
withClockAndReset(clock, reset) { withClockAndReset(clock, reset) {
txd.outputPin(uart.txd) txd.outputPin(uart.txd)
val rxd_t = rxd.inputPin() val rxd_t = rxd.inputPin()
uart.rxd := SynchronizerShiftRegInit(rxd_t, n = syncStages, init = Bool(true), name = Some("uart_rxd_sync")) uart.rxd := SyncResetSynchronizerShiftReg(rxd_t, syncStages, init = Bool(true), name = Some("uart_rxd_sync"))
} }
} }
} }