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shiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate

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This commit is contained in:
Megan Wachs
2017-09-06 10:59:07 -07:00
parent 4381e395af
commit 97c3fcb4b6
3 changed files with 6 additions and 6 deletions
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2
src/main/scala/devices/spi/SPIPhysical.scala
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@ -2,7 +2,7 @@
package sifive.blocks.devices.spi
import Chisel._
import freechipchips.rocketchip.util.ShiftRegInit
import freechips.rocketchip.util.ShiftRegInit
class SPIMicroOp(c: SPIParamsBase) extends SPIBundle(c) {
val fn = Bits(width = 1)