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xilinx mig: track changes in rocket-chip

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This commit is contained in:
Wesley W. Terpstra 2017-02-03 18:17:58 -08:00
parent c010a1557a
commit 88e4c8ee20
1 changed files with 1 additions and 1 deletions
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src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
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@ -11,7 +11,7 @@ trait PeripheryXilinxVC707MIG extends TopNetwork {
val xilinxvc707mig = LazyModule(new XilinxVC707MIG) val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
require(p(BankedL2Config).nMemoryChannels == 1, "Coreplex must have 1 master memory port") require(p(BankedL2Config).nMemoryChannels == 1, "Coreplex must have 1 master memory port")
val mem = Seq(xilinxvc707mig.node) xilinxvc707mig.node := mem(0).node
} }
trait PeripheryXilinxVC707MIGBundle extends TopNetworkBundle { trait PeripheryXilinxVC707MIGBundle extends TopNetworkBundle {