From 88e4c8ee2083559c68c01cc4ea8340b4dfd03d54 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Fri, 3 Feb 2017 18:17:58 -0800
Subject: [PATCH] xilinx mig: track changes in rocket-chip

---
 .../scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala  | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
index b52b37c..4586949 100644
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
@@ -11,7 +11,7 @@ trait PeripheryXilinxVC707MIG extends TopNetwork {
 
   val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
   require(p(BankedL2Config).nMemoryChannels == 1, "Coreplex must have 1 master memory port")
-  val mem = Seq(xilinxvc707mig.node)
+  xilinxvc707mig.node := mem(0).node
 }
 
 trait PeripheryXilinxVC707MIGBundle extends TopNetworkBundle {