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mig: fix MemoryDevice to use 'reg' properly

This commit is contained in:
Wesley W. Terpstra 2017-06-29 13:41:30 -07:00
parent a8e20f447c
commit 886680af49

View File

@ -24,7 +24,7 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters( val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters( slaves = Seq(AXI4SlaveParameters(
address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)), address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
resources = device.reg("mem"), resources = device.reg,
regionType = RegionType.UNCACHED, regionType = RegionType.UNCACHED,
executable = true, executable = true,
supportsWrite = TransferSizes(1, 256*8), supportsWrite = TransferSizes(1, 256*8),