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mig: fix MemoryDevice to use 'reg' properly

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This commit is contained in:
Wesley W. Terpstra
2017-06-29 13:41:30 -07:00
parent a8e20f447c
commit 886680af49
1 changed files with 1 additions and 1 deletions
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src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
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@@ -24,7 +24,7 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
resources = device.reg("mem"),
resources = device.reg,
regionType = RegionType.UNCACHED,
executable = true,
supportsWrite = TransferSizes(1, 256*8),