spi: Fix off-by-one error in calculating cycles per data frame
Issue: Configuring the frame length to certain values causes incorrect operation. Symptoms: Certain frame lengths result in the master sending one extra clock pulse. The slave device may then become desynchronized. Workaround: The following frame lengths are supported and can be used. Do not use other frame lengths. * Serial mode: 0, 2, 4, 6, 8 * Dual mode: 0, 1, 3, 5, 7, 8 * Quad mode: 0, 1, 2, 3, 5, 6, 7, 8
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@ -41,7 +41,7 @@ class SPIFIFO(c: SPIParamsBase) extends Module {
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val proto = SPIProtocol.decode(io.link.fmt.proto).zipWithIndex
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val cnt_quot = Mux1H(proto.map { case (s, i) => s -> (io.ctrl.fmt.len >> i) })
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val cnt_rmdr = Mux1H(proto.map { case (s, i) => s -> (io.ctrl.fmt.len(i, 0).orR) })
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val cnt_rmdr = Mux1H(proto.map { case (s, i) => s -> (if (i > 0) io.ctrl.fmt.len(i-1, 0).orR else UInt(0)) })
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io.link.fmt <> io.ctrl.fmt
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io.link.cnt := cnt_quot + cnt_rmdr
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