riscv/sifive-blocks
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Made regs 32-bit word aligned to match the rest of the system

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This commit is contained in:
Alex Solomatnikov 2017-02-09 11:36:19 -08:00
parent 9ca71c0cf2
commit 72e4b60d81
1 changed files with 4 additions and 4 deletions
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8
src/main/scala/devices/i2c/I2CCtrlRegs.scala
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@ -6,8 +6,8 @@ package sifive.blocks.devices.i2c
object I2CCtrlRegs {
val prescaler_lo = 0x00 // low byte clock prescaler register
val prescaler_hi = 0x01 // high byte clock prescaler register
val control = 0x02 // control register
val data = 0x03 // write: transmit byte, read: receive byte
val cmd_status = 0x04 // write: command, read: status
val prescaler_hi = 0x04 // high byte clock prescaler register
val control = 0x08 // control register
val data = 0x0c // write: transmit byte, read: receive byte
val cmd_status = 0x10 // write: command, read: status
}