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vc707 axi enhancements (#24)

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1 - Print AXI-ID mappings
2 - Use half as many Deinterleaver buffers for the L2 backside
3 - Limit the Q depth on the PCIe control port to 2 (was 1584!)
This commit is contained in:
Wesley W. Terpstra 2017-06-30 12:36:33 -07:00 committed by GitHub
parent 886680af49
commit 66b2fd11bd
2 changed files with 3 additions and 3 deletions
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2
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
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@ -32,7 +32,7 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
beatBytes = 8))) beatBytes = 8)))
val xing = LazyModule(new TLAsyncCrossing) val xing = LazyModule(new TLAsyncCrossing)
val toaxi4 = LazyModule(new TLToAXI4(beatBytes = 8)) val toaxi4 = LazyModule(new TLToAXI4(beatBytes = 8, adapterName = Some("mem"), stripBits = 1))
val indexer = LazyModule(new AXI4IdIndexer(idBits = 4)) val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
val deint = LazyModule(new AXI4Deinterleaver(p(coreplex.CacheBlockBytes))) val deint = LazyModule(new AXI4Deinterleaver(p(coreplex.CacheBlockBytes)))
val yank = LazyModule(new AXI4UserYanker) val yank = LazyModule(new AXI4UserYanker)

4
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
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@ -32,13 +32,13 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
AXI4UserYanker()( AXI4UserYanker()(
AXI4Deinterleaver(p(coreplex.CacheBlockBytes))( AXI4Deinterleaver(p(coreplex.CacheBlockBytes))(
AXI4IdIndexer(idBits=4)( AXI4IdIndexer(idBits=4)(
TLToAXI4(beatBytes=8)( TLToAXI4(beatBytes=8, adapterName = Some("pcie-slave"))(
TLAsyncCrossingSink()( TLAsyncCrossingSink()(
slave)))))) slave))))))
axi_to_pcie_x1.control := axi_to_pcie_x1.control :=
AXI4Buffer()( AXI4Buffer()(
AXI4UserYanker()( AXI4UserYanker(capMaxFlight = Some(2))(
TLToAXI4(beatBytes=4)( TLToAXI4(beatBytes=4)(
TLFragmenter(4, p(coreplex.CacheBlockBytes))( TLFragmenter(4, p(coreplex.CacheBlockBytes))(
TLAsyncCrossingSink()( TLAsyncCrossingSink()(