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Merge pull request #4 from sifive/periphery-keys

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This commit is contained in:
Wesley W. Terpstra 2017-03-02 21:00:44 -08:00 committed by GitHub
commit 64bff44462
26 changed files with 313 additions and 300 deletions
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32
src/main/scala/devices/gpio/GPIO.scala
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@ -2,19 +2,12 @@
package sifive.blocks.devices.gpio
import Chisel._
import config._
import config.Parameters
import regmapper._
import uncore.tilelink2._
import rocketchip.PeripheryBusConfig
import util.AsyncResetRegVec
case class GPIOConfig(address: BigInt, width: Int)
trait HasGPIOParameters {
implicit val p: Parameters
val params: GPIOConfig
val c = params
}
case class GPIOParams(address: BigInt, width: Int)
// YAGNI: Make the PUE, DS, and
// these also optionally HW controllable.
@ -100,7 +93,7 @@ class GPIOPin extends Bundle {
// level, and we have to do the pinmux
// outside of RocketChipTop.
class GPIOPortIO(c: GPIOConfig) extends Bundle {
class GPIOPortIO(c: GPIOParams) extends Bundle {
val pins = Vec(c.width, new GPIOPin)
val iof_0 = Vec(c.width, new GPIOPinIOF).flip
val iof_1 = Vec(c.width, new GPIOPinIOF).flip
@ -108,12 +101,15 @@ class GPIOPortIO(c: GPIOConfig) extends Bundle {
// It would be better if the IOF were here and
// we could do the pinmux inside.
trait GPIOBundle extends Bundle with HasGPIOParameters {
val port = new GPIOPortIO(c)
trait HasGPIOBundleContents extends Bundle {
val params: GPIOParams
val port = new GPIOPortIO(params)
}
trait GPIOModule extends Module with HasGPIOParameters with HasRegMap {
val io: GPIOBundle
trait HasGPIOModuleContents extends Module with HasRegMap {
val io: HasGPIOBundleContents
val params: GPIOParams
val c = params
//--------------------------------------------------
// CSR Declarations
@ -289,7 +285,7 @@ object GPIOInputPinCtrl {
}
// Magic TL2 Incantation to create a TL2 Slave
class TLGPIO(c: GPIOConfig)(implicit p: Parameters)
extends TLRegisterRouter(c.address, interrupts = c.width, beatBytes = p(PeripheryBusConfig).beatBytes)(
new TLRegBundle(c, _) with GPIOBundle)(
new TLRegModule(c, _, _) with GPIOModule)
class TLGPIO(w: Int, c: GPIOParams)(implicit p: Parameters)
extends TLRegisterRouter(c.address, "gpio", Seq("sifive,gpio0"), interrupts = c.width, beatBytes = w)(
new TLRegBundle(c, _) with HasGPIOBundleContents)(
new TLRegModule(c, _, _) with HasGPIOModuleContents)

32
src/main/scala/devices/gpio/GPIOPeriphery.scala
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@ -2,27 +2,31 @@
package sifive.blocks.devices.gpio
import Chisel._
import config.Field
import diplomacy.LazyModule
import rocketchip.{TopNetwork,TopNetworkModule}
import rocketchip.{
HasTopLevelNetworks,
HasTopLevelNetworksBundle,
HasTopLevelNetworksModule
}
import uncore.tilelink2.TLFragmenter
trait PeripheryGPIO {
this: TopNetwork { val gpioConfig: GPIOConfig } =>
val gpio = LazyModule(new TLGPIO(gpioConfig))
gpio.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
case object PeripheryGPIOKey extends Field[GPIOParams]
trait HasPeripheryGPIO extends HasTopLevelNetworks {
val gpioParams = p(PeripheryGPIOKey)
val gpio = LazyModule(new TLGPIO(peripheryBusBytes, gpioParams))
gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := gpio.intnode
}
trait PeripheryGPIOBundle {
this: { val gpioConfig: GPIOConfig } =>
val gpio = new GPIOPortIO(gpioConfig)
trait HasPeripheryGPIOBundle extends HasTopLevelNetworksBundle {
val outer: HasPeripheryGPIO
val gpio = new GPIOPortIO(outer.gpioParams)
}
trait PeripheryGPIOModule {
this: TopNetworkModule {
val gpioConfig: GPIOConfig
val outer: PeripheryGPIO
val io: PeripheryGPIOBundle
} =>
trait HasPeripheryGPIOModule extends HasTopLevelNetworksModule {
val outer: HasPeripheryGPIO
val io: HasPeripheryGPIOBundle
io.gpio <> outer.gpio.module.io.port
}

39
src/main/scala/devices/i2c/I2C.scala
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@ -43,20 +43,12 @@ package sifive.blocks.devices.i2c
import Chisel._
import config._
import util._
import regmapper._
import uncore.tilelink2._
import rocketchip.PeripheryBusConfig
import util.AsyncResetRegVec
import util.{AsyncResetRegVec, Majority}
import sifive.blocks.devices.gpio.{GPIOPinCtrl}
case class I2CConfig(address: BigInt)
trait HasI2CParameters {
implicit val p: Parameters
val params: I2CConfig
val c = params
}
case class I2CParams(address: BigInt)
class I2CPin extends Bundle {
val in = Bool(INPUT)
@ -69,12 +61,13 @@ class I2CPort extends Bundle {
val sda = new I2CPin
}
trait I2CBundle extends Bundle with HasI2CParameters {
trait HasI2CBundleContents extends Bundle {
val port = new I2CPort
}
trait I2CModule extends Module with HasI2CParameters with HasRegMap {
val io: I2CBundle
trait HasI2CModuleContents extends Module with HasRegMap {
val io: HasI2CBundleContents
val params: I2CParams
val I2C_CMD_NOP = UInt(0x00)
val I2C_CMD_START = UInt(0x01)
@ -143,8 +136,8 @@ trait I2CModule extends Module with HasI2CParameters with HasRegMap {
fSDA := Cat(fSDA, io.port.sda.in)
}
val sSCL = Reg(init = true.B, next = (new Majority(fSCL.toBools.toSet)).out)
val sSDA = Reg(init = true.B, next = (new Majority(fSDA.toBools.toSet)).out)
val sSCL = Reg(init = true.B, next = Majority(fSCL))
val sSDA = Reg(init = true.B, next = Majority(fSDA))
val dSCL = Reg(init = true.B, next = sSCL)
val dSDA = Reg(init = true.B, next = sSDA)
@ -540,16 +533,8 @@ trait I2CModule extends Module with HasI2CParameters with HasRegMap {
interrupts(0) := status.irqFlag & control.intEn
}
// Copied from UART.scala
class Majority(in: Set[Bool]) {
private val n = (in.size >> 1) + 1
private val clauses = in.subsets(n).map(_.reduce(_ && _))
val out = clauses.reduce(_ || _)
}
// Magic TL2 Incantation to create a TL2 Slave
class TLI2C(c: I2CConfig)(implicit p: Parameters)
extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = p(PeripheryBusConfig).beatBytes)(
new TLRegBundle(c, _) with I2CBundle)(
new TLRegModule(c, _, _) with I2CModule)
class TLI2C(w: Int, c: I2CParams)(implicit p: Parameters)
extends TLRegisterRouter(c.address, "i2c", Seq("sifive,i2c0"), interrupts = 1, beatBytes = w)(
new TLRegBundle(c, _) with HasI2CBundleContents)(
new TLRegModule(c, _, _) with HasI2CModuleContents)

30
src/main/scala/devices/i2c/I2CPeriphery.scala
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@ -2,31 +2,31 @@
package sifive.blocks.devices.i2c
import Chisel._
import config.Field
import diplomacy.LazyModule
import rocketchip.{TopNetwork,TopNetworkModule}
import rocketchip.{HasTopLevelNetworks,HasTopLevelNetworksBundle,HasTopLevelNetworksModule}
import uncore.tilelink2.TLFragmenter
trait PeripheryI2C {
this: TopNetwork { val i2cConfigs: Seq[I2CConfig] } =>
val i2c = i2cConfigs.zipWithIndex.map { case (c, i) =>
val i2c = LazyModule(new TLI2C(c))
i2c.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
case object PeripheryI2CKey extends Field[Seq[I2CParams]]
trait HasPeripheryI2C extends HasTopLevelNetworks {
val i2cParams = p(PeripheryI2CKey)
val i2c = i2cParams map { params =>
val i2c = LazyModule(new TLI2C(peripheryBusBytes, params))
i2c.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := i2c.intnode
i2c
}
}
trait PeripheryI2CBundle {
this: { val i2cConfigs: Seq[I2CConfig] } =>
val i2cs = Vec(i2cConfigs.size, new I2CPort)
trait HasPeripheryI2CBundle extends HasTopLevelNetworksBundle{
val outer: HasPeripheryI2C
val i2cs = Vec(outer.i2cParams.size, new I2CPort)
}
trait PeripheryI2CModule {
this: TopNetworkModule {
val i2cConfigs: Seq[I2CConfig]
val outer: PeripheryI2C
val io: PeripheryI2CBundle
} =>
trait HasPeripheryI2CModule extends HasTopLevelNetworksModule {
val outer: HasPeripheryI2C
val io: HasPeripheryI2CBundle
(io.i2cs zip outer.i2c).foreach { case (io, device) =>
io <> device.module.io.port
}

27
src/main/scala/devices/mockaon/MockAON.scala
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@ -5,11 +5,10 @@ import Chisel._
import config._
import regmapper._
import uncore.tilelink2._
import rocketchip.PeripheryBusConfig
import sifive.blocks.util.GenericTimer
case class MockAONConfig(
case class MockAONParams(
address: BigInt = BigInt(0x10000000),
nBackupRegs: Int = 16) {
def size: Int = 0x1000
@ -20,12 +19,6 @@ case class MockAONConfig(
def pmuOffset: Int = 0x100
}
trait HasMockAONParameters {
implicit val p: Parameters
val params: MockAONConfig
val c = params
}
class MockAONPMUIO extends Bundle {
val vddpaden = Bool(OUTPUT)
val dwakeup = Bool(INPUT)
@ -36,10 +29,10 @@ class MockAONMOffRstIO extends Bundle {
val corerst = Bool(OUTPUT)
}
trait MockAONBundle extends Bundle with HasMockAONParameters {
trait HasMockAONBundleContents extends Bundle {
// Output of the Power Management Sequencer
val moff = new MockAONMOffRstIO ()
val moff = new MockAONMOffRstIO
// This goes out to wrapper
// to be combined to create aon_rst.
@ -56,8 +49,10 @@ trait MockAONBundle extends Bundle with HasMockAONParameters {
val resetCauses = new ResetCauses().asInput
}
trait MockAONModule extends Module with HasRegMap with HasMockAONParameters {
val io: MockAONBundle
trait HasMockAONModuleContents extends Module with HasRegMap {
val io: HasMockAONBundleContents
val params: MockAONParams
val c = params
// the expectation here is that Chisel's implicit reset is aonrst,
// which is asynchronous, so don't use synchronous-reset registers.
@ -99,7 +94,7 @@ trait MockAONModule extends Module with HasRegMap with HasMockAONParameters {
}
class MockAON(c: MockAONConfig)(implicit p: Parameters)
extends TLRegisterRouter(c.address, interrupts = 2, size = c.size, beatBytes = p(PeripheryBusConfig).beatBytes, concurrency = 1)(
new TLRegBundle(c, _) with MockAONBundle)(
new TLRegModule(c, _, _) with MockAONModule)
class TLMockAON(w: Int, c: MockAONParams)(implicit p: Parameters)
extends TLRegisterRouter(c.address, "aon", Seq("sifive,aon0"), interrupts = 2, size = c.size, beatBytes = w, concurrency = 1)(
new TLRegBundle(c, _) with HasMockAONBundleContents)(
new TLRegModule(c, _, _) with HasMockAONModuleContents)

29
src/main/scala/devices/mockaon/MockAONPeriphery.scala
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@ -2,33 +2,38 @@
package sifive.blocks.devices.mockaon
import Chisel._
import config.Field
import coreplex.CoreplexRISCVPlatform
import diplomacy.LazyModule
import rocketchip.{TopNetwork,TopNetworkModule}
import rocketchip.{
HasTopLevelNetworks,
HasTopLevelNetworksBundle,
HasTopLevelNetworksModule
}
import uncore.tilelink2.{IntXing, TLAsyncCrossingSource, TLFragmenter}
import coreplex._
trait PeripheryMockAON extends TopNetwork {
val mockAONConfig: MockAONConfig
case object PeripheryMockAONKey extends Field[MockAONParams]
trait HasPeripheryMockAON extends HasTopLevelNetworks {
val coreplex: CoreplexRISCVPlatform
// We override the clock & Reset here so that all synchronizers, etc
// are in the proper clock domain.
val aon = LazyModule(new MockAONWrapper(mockAONConfig))
val mockAONParams= p(PeripheryMockAONKey)
val aon = LazyModule(new MockAONWrapper(peripheryBusBytes, mockAONParams))
val aon_int = LazyModule(new IntXing)
aon.node := TLAsyncCrossingSource()(TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node))
aon.node := TLAsyncCrossingSource()(TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node))
aon_int.intnode := aon.intnode
intBus.intnode := aon_int.intnode
}
trait PeripheryMockAONBundle {
trait HasPeripheryMockAONBundle extends HasTopLevelNetworksBundle {
val aon = new MockAONWrapperBundle()
}
trait PeripheryMockAONModule {
this: TopNetworkModule {
val outer: PeripheryMockAON
val io: PeripheryMockAONBundle
} =>
trait HasPeripheryMockAONModule extends HasTopLevelNetworksModule {
val outer: HasPeripheryMockAON
val io: HasPeripheryMockAONBundle
io.aon <> outer.aon.module.io

4
src/main/scala/devices/mockaon/MockAONWrapper.scala
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@ -27,11 +27,11 @@ class MockAONWrapperBundle extends Bundle {
val rsts = new MockAONMOffRstIO()
}
class MockAONWrapper(c: MockAONConfig)(implicit p: Parameters) extends LazyModule {
class MockAONWrapper(w: Int, c: MockAONParams)(implicit p: Parameters) extends LazyModule {
val node = TLAsyncInputNode()
val intnode = IntOutputNode()
val aon = LazyModule (new MockAON(c)(p))
val aon = LazyModule(new TLMockAON(w, c))
// We only need to isolate the signals
// coming from MOFF to AON,

35
src/main/scala/devices/pwm/PWM.scala
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@ -3,9 +3,8 @@ package sifive.blocks.devices.pwm
import Chisel._
import Chisel.ImplicitConversions._
import config._
import config.Parameters
import regmapper._
import rocketchip.PeripheryBusConfig
import uncore.tilelink2._
import util._
@ -13,7 +12,7 @@ import sifive.blocks.util.GenericTimer
// Core PWM Functionality & Register Interface
class PWM(val ncmp: Int = 4, val cmpWidth: Int = 16)(implicit p: Parameters) extends GenericTimer {
class PWM(val ncmp: Int = 4, val cmpWidth: Int = 16) extends GenericTimer {
protected def countWidth = ((1 << scaleWidth) - 1) + cmpWidth
protected lazy val countAlways = RegEnable(io.regs.cfg.write.bits(12), Bool(false), io.regs.cfg.write.valid && unlocked)
protected lazy val feed = count.carryOut(scale + UInt(cmpWidth))
@ -38,35 +37,31 @@ class PWM(val ncmp: Int = 4, val cmpWidth: Int = 16)(implicit p: Parameters) ext
countEn := countAlways || oneShot
}
case class PWMConfig(
case class PWMParams(
address: BigInt,
size: Int = 0x1000,
regBytes: Int = 4,
ncmp: Int = 4,
cmpWidth: Int = 16)
trait HasPWMParameters {
implicit val p: Parameters
val params: PWMConfig
val c = params
trait HasPWMBundleContents extends Bundle {
val params: PWMParams
val gpio = Vec(params.ncmp, Bool()).asOutput
}
trait PWMBundle extends Bundle with HasPWMParameters {
val gpio = Vec(c.ncmp, Bool()).asOutput
}
trait HasPWMModuleContents extends Module with HasRegMap {
val io: HasPWMBundleContents
val params: PWMParams
trait PWMModule extends Module with HasRegMap with HasPWMParameters {
val io: PWMBundle
val pwm = Module(new PWM(c.ncmp, c.cmpWidth))
val pwm = Module(new PWM(params.ncmp, params.cmpWidth))
interrupts := pwm.io.ip
io.gpio := pwm.io.gpio
regmap((GenericTimer.timerRegMap(pwm, 0, c.regBytes)):_*)
regmap((GenericTimer.timerRegMap(pwm, 0, params.regBytes)):_*)
}
class TLPWM(c: PWMConfig)(implicit p: Parameters)
extends TLRegisterRouter(c.address, interrupts = c.ncmp, size = c.size, beatBytes = p(PeripheryBusConfig).beatBytes)(
new TLRegBundle(c, _) with PWMBundle)(
new TLRegModule(c, _, _) with PWMModule)
class TLPWM(w: Int, c: PWMParams)(implicit p: Parameters)
extends TLRegisterRouter(c.address, "pwm", Seq("sifive,pwm0"), interrupts = c.ncmp, size = c.size, beatBytes = w)(
new TLRegBundle(c, _) with HasPWMBundleContents)(
new TLRegModule(c, _, _) with HasPWMModuleContents)

45
src/main/scala/devices/pwm/PWMPeriphery.scala
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@ -2,24 +2,28 @@
package sifive.blocks.devices.pwm
import Chisel._
import config._
import config.Field
import diplomacy.LazyModule
import rocketchip.{TopNetwork,TopNetworkModule}
import rocketchip.{
HasTopLevelNetworks,
HasTopLevelNetworksBundle,
HasTopLevelNetworksModule
}
import uncore.tilelink2.TLFragmenter
import util.HeterogeneousBag
import sifive.blocks.devices.gpio._
class PWMPortIO(c: PWMConfig)(implicit p: Parameters) extends Bundle {
class PWMPortIO(c: PWMParams) extends Bundle {
val port = Vec(c.ncmp, Bool()).asOutput
override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
}
class PWMPinsIO(c: PWMConfig)(implicit p: Parameters) extends Bundle {
class PWMPinsIO(c: PWMParams) extends Bundle {
val pwm = Vec(c.ncmp, new GPIOPin)
}
class PWMGPIOPort(c: PWMConfig)(implicit p: Parameters) extends Module {
class PWMGPIOPort(c: PWMParams) extends Module {
val io = new Bundle {
val pwm = new PWMPortIO(c).flip()
val pins = new PWMPinsIO(c)
@ -28,31 +32,28 @@ class PWMGPIOPort(c: PWMConfig)(implicit p: Parameters) extends Module {
GPIOOutputPinCtrl(io.pins.pwm, io.pwm.port.asUInt)
}
trait PeripheryPWM {
this: TopNetwork { val pwmConfigs: Seq[PWMConfig] } =>
case object PeripheryPWMKey extends Field[Seq[PWMParams]]
val pwm = (pwmConfigs.zipWithIndex) map { case (c, i) =>
val pwm = LazyModule(new TLPWM(c))
pwm.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
trait HasPeripheryPWM extends HasTopLevelNetworks {
val pwmParams = p(PeripheryPWMKey)
val pwms = pwmParams map { params =>
val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
pwm.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := pwm.intnode
pwm
}
}
trait PeripheryPWMBundle {
this: {
val p: Parameters
val pwmConfigs: Seq[PWMConfig]
} =>
val pwms = HeterogeneousBag(pwmConfigs.map(new PWMPortIO(_)(p)))
trait HasPeripheryPWMBundle extends HasTopLevelNetworksBundle {
val outer: HasPeripheryPWM
val pwms = HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_)))
}
trait PeripheryPWMModule {
this: TopNetworkModule {
val outer: PeripheryPWM
val io: PeripheryPWMBundle
} =>
(io.pwms.zipWithIndex zip outer.pwm) foreach { case ((io, i), device) =>
trait HasPeripheryPWMModule extends HasTopLevelNetworksModule {
val outer: HasPeripheryPWM
val io: HasPeripheryPWMBundle
(io.pwms zip outer.pwms) foreach { case (io, device) =>
io.port := device.module.io.gpio
}
}

4
src/main/scala/devices/spi/SPIArbiter.scala
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@ -3,11 +3,11 @@ package sifive.blocks.devices.spi
import Chisel._
class SPIInnerIO(c: SPIConfigBase) extends SPILinkIO(c) {
class SPIInnerIO(c: SPIParamsBase) extends SPILinkIO(c) {
val lock = Bool(OUTPUT)
}
class SPIArbiter(c: SPIConfigBase, n: Int) extends Module {
class SPIArbiter(c: SPIParamsBase, n: Int) extends Module {
val io = new Bundle {
val inner = Vec(n, new SPIInnerIO(c)).flip
val outer = new SPILinkIO(c)

18
src/main/scala/devices/spi/SPIBundle.scala
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@ -3,7 +3,7 @@ package sifive.blocks.devices.spi
import Chisel._
abstract class SPIBundle(val c: SPIConfigBase) extends Bundle {
abstract class SPIBundle(val c: SPIParamsBase) extends Bundle {
override def cloneType: SPIBundle.this.type =
this.getClass.getConstructors.head.newInstance(c).asInstanceOf[this.type]
}
@ -14,7 +14,7 @@ class SPIDataIO extends Bundle {
val oe = Bool(OUTPUT)
}
class SPIPortIO(c: SPIConfigBase) extends SPIBundle(c) {
class SPIPortIO(c: SPIParamsBase) extends SPIBundle(c) {
val sck = Bool(OUTPUT)
val dq = Vec(4, new SPIDataIO)
val cs = Vec(c.csWidth, Bool(OUTPUT))
@ -26,7 +26,7 @@ trait HasSPIProtocol {
trait HasSPIEndian {
val endian = Bits(width = SPIEndian.width)
}
class SPIFormat(c: SPIConfigBase) extends SPIBundle(c)
class SPIFormat(c: SPIParamsBase) extends SPIBundle(c)
with HasSPIProtocol
with HasSPIEndian {
val iodir = Bits(width = SPIDirection.width)
@ -36,13 +36,13 @@ trait HasSPILength extends SPIBundle {
val len = UInt(width = c.lengthBits)
}
class SPIClocking(c: SPIConfigBase) extends SPIBundle(c) {
class SPIClocking(c: SPIParamsBase) extends SPIBundle(c) {
val div = UInt(width = c.divisorBits)
val pol = Bool()
val pha = Bool()
}
class SPIChipSelect(c: SPIConfigBase) extends SPIBundle(c) {
class SPIChipSelect(c: SPIParamsBase) extends SPIBundle(c) {
val id = UInt(width = c.csIdBits)
val dflt = Vec(c.csWidth, Bool())
@ -57,19 +57,19 @@ trait HasSPICSMode {
val mode = Bits(width = SPICSMode.width)
}
class SPIDelay(c: SPIConfigBase) extends SPIBundle(c) {
class SPIDelay(c: SPIParamsBase) extends SPIBundle(c) {
val cssck = UInt(width = c.delayBits)
val sckcs = UInt(width = c.delayBits)
val intercs = UInt(width = c.delayBits)
val interxfr = UInt(width = c.delayBits)
}
class SPIWatermark(c: SPIConfigBase) extends SPIBundle(c) {
class SPIWatermark(c: SPIParamsBase) extends SPIBundle(c) {
val tx = UInt(width = c.txDepthBits)
val rx = UInt(width = c.rxDepthBits)
}
class SPIControl(c: SPIConfigBase) extends SPIBundle(c) {
class SPIControl(c: SPIParamsBase) extends SPIBundle(c) {
val fmt = new SPIFormat(c) with HasSPILength
val sck = new SPIClocking(c)
val cs = new SPIChipSelect(c) with HasSPICSMode
@ -78,7 +78,7 @@ class SPIControl(c: SPIConfigBase) extends SPIBundle(c) {
}
object SPIControl {
def init(c: SPIConfigBase): SPIControl = {
def init(c: SPIParamsBase): SPIControl = {
val ctrl = Wire(new SPIControl(c))
ctrl.fmt.proto := SPIProtocol.Single
ctrl.fmt.iodir := SPIDirection.Rx

4
src/main/scala/devices/spi/SPIFIFO.scala
View File

@ -3,13 +3,13 @@ package sifive.blocks.devices.spi
import Chisel._
class SPIFIFOControl(c: SPIConfigBase) extends SPIBundle(c) {
class SPIFIFOControl(c: SPIParamsBase) extends SPIBundle(c) {
val fmt = new SPIFormat(c) with HasSPILength
val cs = new Bundle with HasSPICSMode
val wm = new SPIWatermark(c)
}
class SPIFIFO(c: SPIConfigBase) extends Module {
class SPIFIFO(c: SPIParamsBase) extends Module {
val io = new Bundle {
val ctrl = new SPIFIFOControl(c).asInput
val link = new SPIInnerIO(c)

10
src/main/scala/devices/spi/SPIFlash.scala
View File

@ -3,7 +3,7 @@ package sifive.blocks.devices.spi
import Chisel._
class SPIFlashInsn(c: SPIFlashConfigBase) extends SPIBundle(c) {
class SPIFlashInsn(c: SPIFlashParamsBase) extends SPIBundle(c) {
val cmd = new Bundle with HasSPIProtocol {
val code = Bits(width = c.insnCmdBits)
val en = Bool()
@ -18,13 +18,13 @@ class SPIFlashInsn(c: SPIFlashConfigBase) extends SPIBundle(c) {
val data = new Bundle with HasSPIProtocol
}
class SPIFlashControl(c: SPIFlashConfigBase) extends SPIBundle(c) {
class SPIFlashControl(c: SPIFlashParamsBase) extends SPIBundle(c) {
val insn = new SPIFlashInsn(c)
val fmt = new Bundle with HasSPIEndian
}
object SPIFlashInsn {
def init(c: SPIFlashConfigBase): SPIFlashInsn = {
def init(c: SPIFlashParamsBase): SPIFlashInsn = {
val insn = Wire(new SPIFlashInsn(c))
insn.cmd.en := Bool(true)
insn.cmd.code := Bits(0x03)
@ -38,12 +38,12 @@ object SPIFlashInsn {
}
}
class SPIFlashAddr(c: SPIFlashConfigBase) extends SPIBundle(c) {
class SPIFlashAddr(c: SPIFlashParamsBase) extends SPIBundle(c) {
val next = UInt(width = c.insnAddrBits)
val hold = UInt(width = c.insnAddrBits)
}
class SPIFlashMap(c: SPIFlashConfigBase) extends Module {
class SPIFlashMap(c: SPIFlashParamsBase) extends Module {
val io = new Bundle {
val en = Bool(INPUT)
val ctrl = new SPIFlashControl(c).asInput

4
src/main/scala/devices/spi/SPIMedia.scala
View File

@ -3,7 +3,7 @@ package sifive.blocks.devices.spi
import Chisel._
class SPILinkIO(c: SPIConfigBase) extends SPIBundle(c) {
class SPILinkIO(c: SPIParamsBase) extends SPIBundle(c) {
val tx = Decoupled(Bits(width = c.frameBits))
val rx = Valid(Bits(width = c.frameBits)).flip
@ -17,7 +17,7 @@ class SPILinkIO(c: SPIConfigBase) extends SPIBundle(c) {
val active = Bool(INPUT)
}
class SPIMedia(c: SPIConfigBase) extends Module {
class SPIMedia(c: SPIParamsBase) extends Module {
val io = new Bundle {
val port = new SPIPortIO(c)
val ctrl = new Bundle {

64
src/main/scala/devices/spi/SPIPeriphery.scala
View File

@ -2,56 +2,58 @@
package sifive.blocks.devices.spi
import Chisel._
import config.Field
import diplomacy.LazyModule
import uncore.tilelink2._
import rocketchip.{TopNetwork,TopNetworkModule}
import rocketchip.{
HasTopLevelNetworks,
HasTopLevelNetworksBundle,
HasTopLevelNetworksModule
}
import uncore.tilelink2.{TLFragmenter, TLWidthWidget}
import util.HeterogeneousBag
trait PeripherySPI {
this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
val spi = (spiConfigs.zipWithIndex) map {case (c, i) =>
val spi = LazyModule(new TLSPI(c))
spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
case object PeripherySPIKey extends Field[Seq[SPIParams]]
trait HasPeripherySPI extends HasTopLevelNetworks {
val spiParams = p(PeripherySPIKey)
val spis = spiParams map { params =>
val spi = LazyModule(new TLSPI(peripheryBusBytes, params))
spi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := spi.intnode
spi
}
}
trait PeripherySPIBundle {
this: { val spiConfigs: Seq[SPIConfig] } =>
val spis = HeterogeneousBag(spiConfigs.map(new SPIPortIO(_)))
trait HasPeripherySPIBundle extends HasTopLevelNetworksBundle {
val outer: HasPeripherySPI
val spis = HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_)))
}
trait PeripherySPIModule {
this: TopNetworkModule {
val spiConfigs: Seq[SPIConfig]
val outer: PeripherySPI
val io: PeripherySPIBundle
} =>
(io.spis zip outer.spi).foreach { case (io, device) =>
trait HasPeripherySPIModule extends HasTopLevelNetworksModule {
val outer: HasPeripherySPI
val io: HasPeripherySPIBundle
(io.spis zip outer.spis).foreach { case (io, device) =>
io <> device.module.io.port
}
}
case object PeripherySPIFlashKey extends Field[SPIFlashParams]
trait PeripherySPIFlash {
this: TopNetwork { val spiFlashConfig: SPIFlashConfig } =>
val qspi = LazyModule(new TLSPIFlash(spiFlashConfig))
qspi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusConfig.beatBytes)(peripheryBus.node))
trait HasPeripherySPIFlash extends HasTopLevelNetworks {
val spiFlashParams = p(PeripherySPIFlashKey)
val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, spiFlashParams))
qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
intBus.intnode := qspi.intnode
}
trait PeripherySPIFlashBundle {
this: { val spiFlashConfig: SPIFlashConfig } =>
val qspi = new SPIPortIO(spiFlashConfig)
trait HasPeripherySPIFlashBundle extends HasTopLevelNetworksBundle {
val outer: HasPeripherySPIFlash
val qspi = new SPIPortIO(outer.spiFlashParams)
}
trait PeripherySPIFlashModule {
this: TopNetworkModule {
val spiConfigs: Seq[SPIConfig]
val outer: PeripherySPIFlash
val io: PeripherySPIFlashBundle
} =>
trait HasPeripherySPIFlashModule extends HasTopLevelNetworksModule {
val outer: HasPeripherySPIFlash
val io: HasPeripherySPIFlashBundle
io.qspi <> outer.qspi.module.io.port
}

6
src/main/scala/devices/spi/SPIPhysical.scala
View File

@ -4,7 +4,7 @@ package sifive.blocks.devices.spi
import Chisel._
import sifive.blocks.util.ShiftRegisterInit
class SPIMicroOp(c: SPIConfigBase) extends SPIBundle(c) {
class SPIMicroOp(c: SPIParamsBase) extends SPIBundle(c) {
val fn = Bits(width = 1)
val stb = Bool()
val cnt = UInt(width = c.countBits)
@ -16,12 +16,12 @@ object SPIMicroOp {
def Delay = UInt(1, 1)
}
class SPIPhyControl(c: SPIConfigBase) extends SPIBundle(c) {
class SPIPhyControl(c: SPIParamsBase) extends SPIBundle(c) {
val sck = new SPIClocking(c)
val fmt = new SPIFormat(c)
}
class SPIPhysical(c: SPIConfigBase) extends Module {
class SPIPhysical(c: SPIParamsBase) extends Module {
val io = new SPIBundle(c) {
val port = new SPIPortIO(c)
val ctrl = new SPIPhyControl(c).asInput

4
src/main/scala/devices/spi/SPIPins.scala
View File

@ -4,13 +4,13 @@ package sifive.blocks.devices.spi
import Chisel._
import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
class SPIPinsIO(c: SPIConfigBase) extends SPIBundle(c) {
class SPIPinsIO(c: SPIParamsBase) extends SPIBundle(c) {
val sck = new GPIOPin
val dq = Vec(4, new GPIOPin)
val cs = Vec(c.csWidth, new GPIOPin)
}
class SPIGPIOPort(c: SPIConfigBase, syncStages: Int = 0, driveStrength: Bool = Bool(false)) extends Module {
class SPIGPIOPort(c: SPIParamsBase, syncStages: Int = 0, driveStrength: Bool = Bool(false)) extends Module {
val io = new SPIBundle(c) {
val spi = new SPIPortIO(c).flip
val pins = new SPIPinsIO(c)

24
src/main/scala/devices/spi/TLSPI.scala
View File

@ -3,14 +3,13 @@ package sifive.blocks.devices.spi
import Chisel._
import config._
import uncore.tilelink2._
import diplomacy._
import regmapper._
import junctions._
import rocketchip.PeripheryBusConfig
import uncore.tilelink2._
import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
trait SPIConfigBase {
trait SPIParamsBase {
val rAddress: BigInt
val rSize: BigInt
val rxDepth: Int
@ -32,7 +31,7 @@ trait SPIConfigBase {
}
case class SPIConfig(
case class SPIParams(
rAddress: BigInt,
rSize: BigInt = 0x1000,
rxDepth: Int = 8,
@ -42,15 +41,15 @@ case class SPIConfig(
delayBits: Int = 8,
divisorBits: Int = 12,
sampleDelay: Int = 2)
extends SPIConfigBase {
extends SPIParamsBase {
require(frameBits >= 4)
require(sampleDelay >= 0)
}
class SPITopBundle(val i: Vec[Vec[Bool]], val r: Vec[TLBundle]) extends Bundle
class SPITopBundle(val i: util.HeterogeneousBag[Vec[Bool]], val r: util.HeterogeneousBag[TLBundle]) extends Bundle
class SPITopModule[B <: SPITopBundle](c: SPIConfigBase, bundle: => B, outer: TLSPIBase)
class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLSPIBase)
extends LazyModuleImp(outer) {
val io = new Bundle {
@ -108,13 +107,14 @@ class SPITopModule[B <: SPITopBundle](c: SPIConfigBase, bundle: => B, outer: TLS
RegField.r(1, ip.rxwm)))
}
abstract class TLSPIBase(c: SPIConfigBase)(implicit p: Parameters) extends LazyModule {
abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule {
require(isPow2(c.rSize))
val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), beatBytes = p(PeripheryBusConfig).beatBytes)
val intnode = IntSourceNode(1)
val device = new SimpleDevice("spi", Seq("sifive,spi0"))
val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), device = device, beatBytes = w)
val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
}
class TLSPI(c: SPIConfig)(implicit p: Parameters) extends TLSPIBase(c)(p) {
class TLSPI(w: Int, c: SPIParams)(implicit p: Parameters) extends TLSPIBase(w,c)(p) {
lazy val module = new SPITopModule(c, new SPITopBundle(intnode.bundleOut, rnode.bundleIn), this) {
mac.io.link <> fifo.io.link
rnode.regmap(regmapBase:_*)

14
src/main/scala/devices/spi/TLSPIFlash.scala
View File

@ -7,7 +7,7 @@ import diplomacy._
import regmapper._
import uncore.tilelink2._
trait SPIFlashConfigBase extends SPIConfigBase {
trait SPIFlashParamsBase extends SPIParamsBase {
val fAddress: BigInt
val fSize: BigInt
@ -18,7 +18,7 @@ trait SPIFlashConfigBase extends SPIConfigBase {
lazy val insnAddrLenBits = log2Floor(insnAddrBytes) + 1
}
case class SPIFlashConfig(
case class SPIFlashParams(
rAddress: BigInt,
fAddress: BigInt,
rSize: BigInt = 0x1000,
@ -29,7 +29,7 @@ case class SPIFlashConfig(
delayBits: Int = 8,
divisorBits: Int = 12,
sampleDelay: Int = 2)
extends SPIFlashConfigBase {
extends SPIFlashParamsBase {
val frameBits = 8
val insnAddrBytes = 4
val insnPadLenBits = 4
@ -38,10 +38,10 @@ case class SPIFlashConfig(
require(sampleDelay >= 0)
}
class SPIFlashTopBundle(i: Vec[Vec[Bool]], r: Vec[TLBundle], val f: Vec[TLBundle]) extends SPITopBundle(i, r)
class SPIFlashTopBundle(i: util.HeterogeneousBag[Vec[Bool]], r: util.HeterogeneousBag[TLBundle], val f: util.HeterogeneousBag[TLBundle]) extends SPITopBundle(i, r)
class SPIFlashTopModule[B <: SPIFlashTopBundle]
(c: SPIFlashConfigBase, bundle: => B, outer: TLSPIFlashBase)
(c: SPIFlashParamsBase, bundle: => B, outer: TLSPIFlashBase)
extends SPITopModule(c, bundle, outer) {
val flash = Module(new SPIFlashMap(c))
@ -91,7 +91,7 @@ class SPIFlashTopModule[B <: SPIFlashTopBundle]
SPICRs.insnpad -> Seq(RegField(c.frameBits, insn.pad.code)))
}
abstract class TLSPIFlashBase(c: SPIFlashConfigBase)(implicit p: Parameters) extends TLSPIBase(c)(p) {
abstract class TLSPIFlashBase(w: Int, c: SPIFlashParamsBase)(implicit p: Parameters) extends TLSPIBase(w,c)(p) {
require(isPow2(c.fSize))
val fnode = TLManagerNode(1, TLManagerParameters(
address = Seq(AddressSet(c.fAddress, c.fSize-1)),
@ -101,7 +101,7 @@ abstract class TLSPIFlashBase(c: SPIFlashConfigBase)(implicit p: Parameters) ext
fifoId = Some(0)))
}
class TLSPIFlash(c: SPIFlashConfig)(implicit p: Parameters) extends TLSPIFlashBase(c)(p) {
class TLSPIFlash(w: Int, c: SPIFlashParams)(implicit p: Parameters) extends TLSPIFlashBase(w,c)(p) {
lazy val module = new SPIFlashTopModule(c,
new SPIFlashTopBundle(intnode.bundleOut, rnode.bundleIn, fnode.bundleIn), this) {

70
src/main/scala/devices/uart/UART.scala
View File

@ -5,12 +5,11 @@ import Chisel._
import config._
import regmapper._
import uncore.tilelink2._
import junctions._
import util._
import rocketchip.PeripheryBusConfig
import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
case class UARTConfig(
case class UARTParams(
address: BigInt,
dataBits: Int = 8,
stopBits: Int = 2,
@ -21,23 +20,23 @@ case class UARTConfig(
nRxEntries: Int = 8)
trait HasUARTParameters {
val c: UARTConfig
val uartDataBits = c.dataBits
val uartStopBits = c.stopBits
val uartDivisorBits = c.divisorBits
def c: UARTParams
def uartDataBits = c.dataBits
def uartStopBits = c.stopBits
def uartDivisorBits = c.divisorBits
val uartOversample = c.oversample
val uartOversampleFactor = 1 << uartOversample
val uartNSamples = c.nSamples
def uartOversample = c.oversample
def uartOversampleFactor = 1 << uartOversample
def uartNSamples = c.nSamples
val uartNTxEntries = c.nTxEntries
val uartNRxEntries = c.nRxEntries
def uartNTxEntries = c.nTxEntries
def uartNRxEntries = c.nRxEntries
require(uartDivisorBits > uartOversample)
require(uartOversampleFactor > uartNSamples)
}
abstract class UARTModule(val c: UARTConfig)(implicit val p: Parameters)
abstract class UARTModule(val c: UARTParams)(implicit val p: Parameters)
extends Module with HasUARTParameters
class UARTPortIO extends Bundle {
@ -45,17 +44,11 @@ class UARTPortIO extends Bundle {
val rxd = Bool(INPUT)
}
trait MixUARTParameters {
implicit val p: Parameters
val params: UARTConfig
val c = params
}
trait UARTTopBundle extends Bundle with MixUARTParameters with HasUARTParameters {
trait HasUARTTopBundleContents extends Bundle {
val port = new UARTPortIO
}
class UARTTx(c: UARTConfig)(implicit p: Parameters) extends UARTModule(c)(p) {
class UARTTx(c: UARTParams)(implicit p: Parameters) extends UARTModule(c)(p) {
val io = new Bundle {
val en = Bool(INPUT)
val in = Decoupled(Bits(width = uartDataBits)).flip
@ -91,7 +84,7 @@ class UARTTx(c: UARTConfig)(implicit p: Parameters) extends UARTModule(c)(p) {
}
}
class UARTRx(c: UARTConfig)(implicit p: Parameters) extends UARTModule(c)(p) {
class UARTRx(c: UARTParams)(implicit p: Parameters) extends UARTModule(c)(p) {
val io = new Bundle {
val en = Bool(INPUT)
val in = Bits(INPUT, 1)
@ -116,7 +109,7 @@ class UARTRx(c: UARTConfig)(implicit p: Parameters) extends UARTModule(c)(p) {
}
val sample = Reg(Bits(width = uartNSamples))
val voter = new Majority(sample.toBools.toSet)
val voter = Majority(sample.toBools.toSet)
when (pulse) {
sample := Cat(sample, io.in)
}
@ -164,7 +157,7 @@ class UARTRx(c: UARTConfig)(implicit p: Parameters) extends UARTModule(c)(p) {
busy := Bool(true)
when (expire) {
sched := Bool(true)
when (voter.out) {
when (voter) {
state := s_idle
} .otherwise {
state := s_data
@ -181,7 +174,7 @@ class UARTRx(c: UARTConfig)(implicit p: Parameters) extends UARTModule(c)(p) {
state := s_idle
valid := Bool(true)
} .otherwise {
shifter := Cat(voter.out, shifter >> 1)
shifter := Cat(voter, shifter >> 1)
sched := Bool(true)
}
}
@ -198,13 +191,16 @@ class UARTInterrupts extends Bundle {
val txwm = Bool()
}
trait UARTTopModule extends Module with MixUARTParameters with HasUARTParameters with HasRegMap {
val io: UARTTopBundle
trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasRegMap {
val io: HasUARTTopBundleContents
implicit val p: Parameters
def params: UARTParams
def c = params
val txm = Module(new UARTTx(c))
val txm = Module(new UARTTx(params))
val txq = Module(new Queue(txm.io.in.bits, uartNTxEntries))
val rxm = Module(new UARTRx(c))
val rxm = Module(new UARTRx(params))
val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
val divinit = 542 // (62.5MHz / 115200)
@ -262,14 +258,8 @@ trait UARTTopModule extends Module with MixUARTParameters with HasUARTParameters
)
}
class Majority(in: Set[Bool]) {
private val n = (in.size >> 1) + 1
private val clauses = in.subsets(n).map(_.reduce(_ && _))
val out = clauses.reduce(_ || _)
}
// Magic TL2 Incantation to create a TL2 Slave
class UART(c: UARTConfig)(implicit p: Parameters)
extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = p(PeripheryBusConfig).beatBytes)(
new TLRegBundle(c, _) with UARTTopBundle)(
new TLRegModule(c, _, _) with UARTTopModule)
// Magic TL2 Incantation to create a TL2 UART
class TLUART(w: Int, c: UARTParams)(implicit p: Parameters)
extends TLRegisterRouter(c.address, "serial", Seq("sifive,uart0"), interrupts = 1, beatBytes = w)(
new TLRegBundle(c, _) with HasUARTTopBundleContents)(
new TLRegModule(c, _, _) with HasUARTTopModuleContents)

40
src/main/scala/devices/uart/UARTPeriphery.scala
View File

@ -2,37 +2,39 @@
package sifive.blocks.devices.uart
import Chisel._
import config._
import diplomacy._
import config.Field
import diplomacy.LazyModule
import rocketchip.{
HasTopLevelNetworks,
HasTopLevelNetworksBundle,
HasTopLevelNetworksModule
}
import uncore.tilelink2._
import rocketchip._
import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
import sifive.blocks.util.ShiftRegisterInit
trait PeripheryUART {
this: TopNetwork {
val uartConfigs: Seq[UARTConfig]
} =>
val uart = uartConfigs.zipWithIndex.map { case (c, i) =>
val uart = LazyModule(new UART(c))
uart.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
case object PeripheryUARTKey extends Field[Seq[UARTParams]]
trait HasPeripheryUART extends HasTopLevelNetworks {
val uartParams = p(PeripheryUARTKey)
val uarts = uartParams map { params =>
val uart = LazyModule(new TLUART(peripheryBusBytes, params))
uart.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := uart.intnode
uart
}
}
trait PeripheryUARTBundle {
this: { val uartConfigs: Seq[UARTConfig] } =>
val uarts = Vec(uartConfigs.size, new UARTPortIO)
trait HasPeripheryUARTBundle extends HasTopLevelNetworksBundle {
val outer: HasPeripheryUART
val uarts = Vec(outer.uartParams.size, new UARTPortIO)
}
trait PeripheryUARTModule {
this: TopNetworkModule {
val outer: PeripheryUART
val io: PeripheryUARTBundle
} =>
(io.uarts zip outer.uart).foreach { case (io, device) =>
trait HasPeripheryUARTModule extends HasTopLevelNetworksModule {
val outer: HasPeripheryUART
val io: HasPeripheryUARTBundle
(io.uarts zip outer.uarts).foreach { case (io, device) =>
io <> device.module.io.port
}
}

2
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
View File

@ -26,10 +26,12 @@ class XilinxVC707MIGIO extends Bundle with VC707MIGUnidirectionalIODDR
}
class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters {
val device = new MemoryDevice
val node = TLInputNode()
val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
resources = device.reg,
regionType = RegionType.UNCACHED,
executable = true,
supportsWrite = TransferSizes(1, 256*8),

18
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
View File

@ -3,24 +3,28 @@ package sifive.blocks.devices.xilinxvc707mig
import Chisel._
import diplomacy._
import rocketchip.{TopNetwork,TopNetworkModule,TopNetworkBundle}
import rocketchip.{
HasTopLevelNetworks,
HasTopLevelNetworksModule,
HasTopLevelNetworksBundle
}
import coreplex.BankedL2Config
trait PeripheryXilinxVC707MIG extends TopNetwork {
val module: PeripheryXilinxVC707MIGModule
trait HasPeripheryXilinxVC707MIG extends HasTopLevelNetworks {
val module: HasPeripheryXilinxVC707MIGModule
val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
require(p(BankedL2Config).nMemoryChannels == 1, "Coreplex must have 1 master memory port")
xilinxvc707mig.node := mem(0).node
}
trait PeripheryXilinxVC707MIGBundle extends TopNetworkBundle {
trait HasPeripheryXilinxVC707MIGBundle extends HasTopLevelNetworksBundle {
val xilinxvc707mig = new XilinxVC707MIGIO
}
trait PeripheryXilinxVC707MIGModule extends TopNetworkModule {
val outer: PeripheryXilinxVC707MIG
val io: PeripheryXilinxVC707MIGBundle
trait HasPeripheryXilinxVC707MIGModule extends HasTopLevelNetworksModule {
val outer: HasPeripheryXilinxVC707MIG
val io: HasPeripheryXilinxVC707MIGBundle
io.xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
}

4
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
View File

@ -23,12 +23,13 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
val slave = TLInputNode()
val control = TLInputNode()
val master = TLOutputNode()
val intnode = IntSourceNode(1)
val intnode = IntOutputNode()
val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
axi_to_pcie_x1.slave := AXI4Buffer()(TLToAXI4(idBits=4)(slave))
axi_to_pcie_x1.control := AXI4Buffer()(AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control)))
master := TLWidthWidget(8)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master)))
intnode := axi_to_pcie_x1.intnode
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
@ -40,7 +41,6 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
}
io.port <> axi_to_pcie_x1.module.io.port
io.interrupt(0)(0) := axi_to_pcie_x1.module.io.interrupt_out
//PCIe Reference Clock
val ibufds_gte2 = Module(new IBUFDS_GTE2)

18
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
View File

@ -3,25 +3,29 @@ package sifive.blocks.devices.xilinxvc707pciex1
import Chisel._
import diplomacy.LazyModule
import rocketchip.{TopNetwork,TopNetworkModule,TopNetworkBundle}
import rocketchip.{
HasTopLevelNetworks,
HasTopLevelNetworksModule,
HasTopLevelNetworksBundle
}
import uncore.tilelink2.TLWidthWidget
trait PeripheryXilinxVC707PCIeX1 extends TopNetwork {
trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
l2.node := xilinxvc707pcie.master
l2FrontendBus.node := xilinxvc707pcie.master
xilinxvc707pcie.slave := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
intBus.intnode := xilinxvc707pcie.intnode
}
trait PeripheryXilinxVC707PCIeX1Bundle extends TopNetworkBundle {
trait HasPeripheryXilinxVC707PCIeX1Bundle extends HasTopLevelNetworksBundle {
val xilinxvc707pcie = new XilinxVC707PCIeX1IO
}
trait PeripheryXilinxVC707PCIeX1Module extends TopNetworkModule {
val outer: PeripheryXilinxVC707PCIeX1
val io: PeripheryXilinxVC707PCIeX1Bundle
trait HasPeripheryXilinxVC707PCIeX1Module extends HasTopLevelNetworksModule {
val outer: HasPeripheryXilinxVC707PCIeX1
val io: HasPeripheryXilinxVC707PCIeX1Bundle
io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
}

32
src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
View File

@ -5,6 +5,7 @@ import Chisel._
import config._
import diplomacy._
import uncore.axi4._
import uncore.tilelink2.{IntSourceNode, IntSourcePortSimple}
import junctions._
// IP VLNV: xilinx.com:customize_ip:vc707pcietoaxi:1.0
@ -167,9 +168,33 @@ class vc707axi_to_pcie_x1() extends BlackBox
class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
{
val device = new SimpleDevice("pci", Seq("xlnx,axi-pcie-host-1.00.a")) {
override def describe(resources: ResourceBindings): Description = {
val Description(name, mapping) = super.describe(resources)
val intc = "pcie_intc"
def ofInt(x: Int) = Seq(ResourceInt(BigInt(x)))
def ofMap(x: Int) = Seq(0, 0, 0, x).flatMap(ofInt) ++ Seq(ResourceReference(intc)) ++ ofInt(x)
val extra = Map(
"#address-cells" -> ofInt(3),
"#size-cells" -> ofInt(2),
"#interrupt-cells" -> ofInt(1),
"device_type" -> Seq(ResourceString("pci")),
"interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt),
"interrupt-map" -> Seq(1, 2, 3, 4).flatMap(ofMap),
"ranges" -> resources("ranges").map { case Binding(_, ResourceAddress(address, _, _, _)) =>
ResourceMapping(address, 0) },
"interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map(
"interrupt-controller" -> Nil,
"#address-cells" -> ofInt(0),
"#interrupt-cells" -> ofInt(1)))))
Description(name, mapping ++ extra)
}
}
val slave = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(0x60000000L, 0x1fffffffL)),
resources = Seq(Resource(device, "ranges")),
executable = true,
supportsWrite = TransferSizes(1, 256),
supportsRead = TransferSizes(1, 256),
@ -179,6 +204,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(0x50000000L, 0x03ffffffL)),
resources = device.reg,
supportsWrite = TransferSizes(1, 4),
supportsRead = TransferSizes(1, 4),
interleavedId = Some(0))), // no read interleaving b/c AXI-lite
@ -189,6 +215,8 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
id = IdRange(0, 1),
aligned = false)))))
val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
lazy val module = new LazyModuleImp(this) {
// The master on the control port must be AXI-lite
require (control.edgesIn(0).master.endId == 1)
@ -204,7 +232,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
val control_in = control.bundleIn
val master_out = master.bundleOut
val REFCLK = Bool(INPUT)
val interrupt_out = Bool(OUTPUT)
val interrupt_out = intnode.bundleOut
}
val blackbox = Module(new vc707axi_to_pcie_x1)
@ -222,7 +250,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
io.port.pci_exp_txn := blackbox.io.pci_exp_txn
blackbox.io.pci_exp_rxp := io.port.pci_exp_rxp
blackbox.io.pci_exp_rxn := io.port.pci_exp_rxn
io.interrupt_out := blackbox.io.interrupt_out
io.interrupt_out(0)(0) := blackbox.io.interrupt_out
blackbox.io.REFCLK := io.REFCLK
//s