spi: work around ucb-bar/chisel3#472
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@ -5,29 +5,29 @@ import Chisel._
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object SPIProtocol {
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object SPIProtocol {
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val width = 2
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val width = 2
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val Single = UInt(0, width)
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def Single = UInt(0, width)
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val Dual = UInt(1, width)
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def Dual = UInt(1, width)
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val Quad = UInt(2, width)
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def Quad = UInt(2, width)
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val cases = Seq(Single, Dual, Quad)
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def cases = Seq(Single, Dual, Quad)
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def decode(x: UInt): Seq[Bool] = cases.map(_ === x)
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def decode(x: UInt): Seq[Bool] = cases.map(_ === x)
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}
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}
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object SPIDirection {
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object SPIDirection {
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val width = 1
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val width = 1
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val Rx = UInt(0, width)
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def Rx = UInt(0, width)
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val Tx = UInt(1, width)
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def Tx = UInt(1, width)
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}
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}
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object SPIEndian {
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object SPIEndian {
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val width = 1
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val width = 1
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val MSB = UInt(0, width)
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def MSB = UInt(0, width)
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val LSB = UInt(1, width)
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def LSB = UInt(1, width)
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}
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}
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object SPICSMode {
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object SPICSMode {
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val width = 2
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val width = 2
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val Auto = UInt(0, width)
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def Auto = UInt(0, width)
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val Hold = UInt(2, width)
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def Hold = UInt(2, width)
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val Off = UInt(3, width)
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def Off = UInt(3, width)
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}
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}
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@ -12,8 +12,8 @@ class SPIMicroOp(c: SPIConfigBase) extends SPIBundle(c) {
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}
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}
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object SPIMicroOp {
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object SPIMicroOp {
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val Transfer = UInt(0, 1)
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def Transfer = UInt(0, 1)
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val Delay = UInt(1, 1)
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def Delay = UInt(1, 1)
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}
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}
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class SPIPhyControl(c: SPIConfigBase) extends SPIBundle(c) {
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class SPIPhyControl(c: SPIConfigBase) extends SPIBundle(c) {
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