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This commit is contained in:
Wesley W. Terpstra 2017-01-31 14:03:14 -08:00
parent 5b6760394d
commit 535be3e976
2 changed files with 13 additions and 13 deletions

View File

@ -5,29 +5,29 @@ import Chisel._
object SPIProtocol { object SPIProtocol {
val width = 2 val width = 2
val Single = UInt(0, width) def Single = UInt(0, width)
val Dual = UInt(1, width) def Dual = UInt(1, width)
val Quad = UInt(2, width) def Quad = UInt(2, width)
val cases = Seq(Single, Dual, Quad) def cases = Seq(Single, Dual, Quad)
def decode(x: UInt): Seq[Bool] = cases.map(_ === x) def decode(x: UInt): Seq[Bool] = cases.map(_ === x)
} }
object SPIDirection { object SPIDirection {
val width = 1 val width = 1
val Rx = UInt(0, width) def Rx = UInt(0, width)
val Tx = UInt(1, width) def Tx = UInt(1, width)
} }
object SPIEndian { object SPIEndian {
val width = 1 val width = 1
val MSB = UInt(0, width) def MSB = UInt(0, width)
val LSB = UInt(1, width) def LSB = UInt(1, width)
} }
object SPICSMode { object SPICSMode {
val width = 2 val width = 2
val Auto = UInt(0, width) def Auto = UInt(0, width)
val Hold = UInt(2, width) def Hold = UInt(2, width)
val Off = UInt(3, width) def Off = UInt(3, width)
} }

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@ -12,8 +12,8 @@ class SPIMicroOp(c: SPIConfigBase) extends SPIBundle(c) {
} }
object SPIMicroOp { object SPIMicroOp {
val Transfer = UInt(0, 1) def Transfer = UInt(0, 1)
val Delay = UInt(1, 1) def Delay = UInt(1, 1)
} }
class SPIPhyControl(c: SPIConfigBase) extends SPIBundle(c) { class SPIPhyControl(c: SPIConfigBase) extends SPIBundle(c) {