riscv/sifive-blocks
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make some base bundle classes easier to clone (#20)

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This commit is contained in:
Henry Cook 2017-06-14 19:47:56 -07:00 committed by GitHub
parent 90d3931f5a
commit 473464eaa9
2 changed files with 4 additions and 3 deletions
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4
src/main/scala/devices/gpio/GPIO.scala
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@ -5,7 +5,7 @@ import Chisel._
import config.Parameters
import regmapper._
import uncore.tilelink2._
import util.AsyncResetRegVec
import util.{AsyncResetRegVec, GenericParameterizedBundle}
case class GPIOParams(address: BigInt, width: Int)
@ -93,7 +93,7 @@ class GPIOPin extends Bundle {
// level, and we have to do the pinmux
// outside of RocketChipTop.
class GPIOPortIO(c: GPIOParams) extends Bundle {
class GPIOPortIO(c: GPIOParams) extends GenericParameterizedBundle(c) {
val pins = Vec(c.width, new GPIOPin)
val iof_0 = Vec(c.width, new GPIOPinIOF).flip
val iof_1 = Vec(c.width, new GPIOPinIOF).flip

3
src/main/scala/devices/spi/SPIBundle.scala
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@ -2,8 +2,9 @@
package sifive.blocks.devices.spi
import Chisel._
import util.GenericParameterizedBundle
abstract class SPIBundle(val c: SPIParamsBase) extends Bundle {
abstract class SPIBundle(val c: SPIParamsBase) extends GenericParameterizedBundle(c) {
override def cloneType: SPIBundle.this.type =
this.getClass.getConstructors.head.newInstance(c).asInstanceOf[this.type]
}