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Bug fixes: passing OC WB test

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This commit is contained in:
Alex Solomatnikov 2017-02-03 16:41:59 -08:00
parent 2cc1012fa2
commit 3781d1fb1a
1 changed files with 7 additions and 6 deletions
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13
src/main/scala/devices/i2c/I2C.scala
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@ -328,7 +328,7 @@ trait I2CModule extends Module with HasI2CParameters with HasRegMap {
when (load) {
receivedData := transmitData
}
.otherwise {
.elsewhen (shift) {
receivedData := Cat(receivedData, receivedBit)
}
@ -453,6 +453,11 @@ trait I2CModule extends Module with HasI2CParameters with HasRegMap {
//////// Top level ////////
// hack
val nextCmd = Wire(UInt(8.W))
nextCmd := cmd.asUInt
cmd := (new CommandBundle).fromBits(nextCmd)
when (cmdAck || arbLost) {
cmd.start := false.B // clear command bits when done
cmd.stop := false.B // or when aribitration lost
@ -461,6 +466,7 @@ trait I2CModule extends Module with HasI2CParameters with HasRegMap {
}
cmd.irqAck := false.B // clear IRQ_ACK bit (essentially 1 cycle pulse b/c it is overwritten by regmap below)
status.receivedAck := receivedAck
when (stopCond) {
status.busy := false.B
}
@ -477,11 +483,6 @@ trait I2CModule extends Module with HasI2CParameters with HasRegMap {
status.transferInProgress := cmd.read || cmd.write
status.irqFlag := (cmdAck || arbLost || status.irqFlag) && !cmd.irqAck
// hack
val nextCmd = Wire(UInt(8.W))
nextCmd := cmd.asUInt
cmd := (new CommandBundle).fromBits(nextCmd)
// Note that these are out of order.
regmap(
I2CCtrlRegs.prescaler_lo -> Seq(RegField(8, prescaler.lo)),