riscv/sifive-blocks
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SPIFlash: make it listable

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This commit is contained in:
Megan Wachs 2017-06-08 16:29:01 -07:00
parent c89f163c0d
commit 29226701a8
1 changed files with 14 additions and 7 deletions
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15
src/main/scala/devices/spi/SPIPeriphery.scala
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@ -37,23 +37,30 @@ trait HasPeripherySPIModule extends HasTopLevelNetworksModule {
}
}
case object PeripherySPIFlashKey extends Field[SPIFlashParams]
case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
trait HasPeripherySPIFlash extends HasTopLevelNetworks {
val spiFlashParams = p(PeripherySPIFlashKey)
val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, spiFlashParams))
val qspi = spiFlashParams map { params =>
val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params))
qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
intBus.intnode := qspi.intnode
qspi
}
}
trait HasPeripherySPIFlashBundle extends HasTopLevelNetworksBundle {
val outer: HasPeripherySPIFlash
val qspi = new SPIPortIO(outer.spiFlashParams)
val qspi = HeterogenousBag(outer.spiFlashParams.map(new SPIPortIO(_)))
}
trait HasPeripherySPIFlashModule extends HasTopLevelNetworksModule {
val outer: HasPeripherySPIFlash
val io: HasPeripherySPIFlashBundle
io.qspi <> outer.qspi.module.io.port
(io.qspi zip outer.qspi) foreach { case (io, device) =>
io.qspi <> device.module.io.port
}
}