67 lines
2.0 KiB
Scala
67 lines
2.0 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.spi
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import Chisel._
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import config.Field
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import diplomacy.LazyModule
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import rocketchip.{
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HasTopLevelNetworks,
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HasTopLevelNetworksBundle,
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HasTopLevelNetworksModule
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}
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import uncore.tilelink2.{TLFragmenter, TLWidthWidget}
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import util.HeterogeneousBag
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case object PeripherySPIKey extends Field[Seq[SPIParams]]
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trait HasPeripherySPI extends HasTopLevelNetworks {
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val spiParams = p(PeripherySPIKey)
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val spis = spiParams map { params =>
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val spi = LazyModule(new TLSPI(peripheryBusBytes, params))
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spi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
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intBus.intnode := spi.intnode
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spi
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}
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}
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trait HasPeripherySPIBundle extends HasTopLevelNetworksBundle {
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val outer: HasPeripherySPI
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val spis = HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_)))
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}
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trait HasPeripherySPIModule extends HasTopLevelNetworksModule {
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val outer: HasPeripherySPI
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val io: HasPeripherySPIBundle
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(io.spis zip outer.spis).foreach { case (io, device) =>
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io <> device.module.io.port
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}
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}
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case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
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trait HasPeripherySPIFlash extends HasTopLevelNetworks {
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val spiFlashParams = p(PeripherySPIFlashKey)
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val qspi = spiFlashParams map { params =>
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val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params))
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qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
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qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
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intBus.intnode := qspi.intnode
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qspi
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}
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}
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trait HasPeripherySPIFlashBundle extends HasTopLevelNetworksBundle {
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val outer: HasPeripherySPIFlash
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val qspi = HeterogenousBag(outer.spiFlashParams.map(new SPIPortIO(_)))
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}
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trait HasPeripherySPIFlashModule extends HasTopLevelNetworksModule {
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val outer: HasPeripherySPIFlash
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val io: HasPeripherySPIFlashBundle
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(io.qspi zip outer.qspi) foreach { case (io, device) =>
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io.qspi <> device.module.io.port
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}
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}
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