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xilinx pcie: bytes, not bits

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This bug amazingly compiled correctly and ran correctly!

It was saved by the AXIFragmenter which turned the "narrow burst" into
individual beats that then got converted to 64b in TileLink land via
inspection of the mask bits.

The consequence is that AXI bus mastering proceeded at one word per
DDR round-trip. Now it is one cache line per DDR round-trip. When we
get L2 back in the design, it should really fly!
This commit is contained in:
Wesley W. Terpstra 2016-12-06 16:13:12 -08:00
parent ca7555bd4d
commit 1443834186
1 changed files with 1 additions and 1 deletions
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src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
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@ -28,7 +28,7 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1) val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
axi_to_pcie_x1.slave := TLToAXI4(idBits=4)(slave) axi_to_pcie_x1.slave := TLToAXI4(idBits=4)(slave)
axi_to_pcie_x1.control := AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control)) axi_to_pcie_x1.control := AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control))
master := TLWidthWidget(64)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master))) master := TLWidthWidget(8)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master)))
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {
val io = new Bundle { val io = new Bundle {