From 1443834186bad8981ed29801d3703c05218ce6dc Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 6 Dec 2016 16:13:12 -0800 Subject: [PATCH] xilinx pcie: bytes, not bits This bug amazingly compiled correctly and ran correctly! It was saved by the AXIFragmenter which turned the "narrow burst" into individual beats that then got converted to 64b in TileLink land via inspection of the mask bits. The consequence is that AXI bus mastering proceeded at one word per DDR round-trip. Now it is one cache line per DDR round-trip. When we get L2 back in the design, it should really fly! --- .../scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala index a795bf0..bd3b1ef 100644 --- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala +++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala @@ -28,7 +28,7 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule { val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1) axi_to_pcie_x1.slave := TLToAXI4(idBits=4)(slave) axi_to_pcie_x1.control := AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control)) - master := TLWidthWidget(64)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master))) + master := TLWidthWidget(8)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master))) lazy val module = new LazyModuleImp(this) { val io = new Bundle {