riscv/sifive-blocks
1
0
Fork 0
Code Releases Activity

uart: power-on with the right divider for the design (#15)

Browse Source
This commit is contained in:
Wesley W. Terpstra 2017-05-13 23:38:20 -07:00 committed by GitHub
parent 9c8fe44670
commit 0f8722f80c
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/devices/uart/UART.scala
View File

@ -203,7 +203,7 @@ trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg
val rxm = Module(new UARTRx(params)) val rxm = Module(new UARTRx(params))
val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries)) val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
val divinit = 542 // (62.5MHz / 115200) val divinit = p(diplomacy.DTSTimebase) * p(rocketchip.RTCPeriod) / 115200
val div = Reg(init = UInt(divinit, uartDivisorBits)) val div = Reg(init = UInt(divinit, uartDivisorBits))
private val stopCountBits = log2Up(uartStopBits) private val stopCountBits = log2Up(uartStopBits)