riscv/sifive-blocks
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Merge remote-tracking branch 'origin/master' into typed_pad_ctrl

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This commit is contained in:
Megan Wachs
2017-07-24 09:17:53 -07:00
parent 2bad829e6e 9ae6413273
commit 0a80d1987d
10 changed files with 71 additions and 76 deletions
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23
src/main/scala/devices/spi/SPIPeriphery.scala
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@ -3,19 +3,19 @@ package sifive.blocks.devices.spi
import Chisel._
import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
import freechips.rocketchip.chip.HasSystemNetworks
import freechips.rocketchip.tilelink.{TLFragmenter,TLWidthWidget}
import freechips.rocketchip.tilelink.{TLFragmenter}
import freechips.rocketchip.util.HeterogeneousBag
case object PeripherySPIKey extends Field[Seq[SPIParams]]
trait HasPeripherySPI extends HasSystemNetworks {
trait HasPeripherySPI extends HasPeripheryBus with HasInterruptBus {
val spiParams = p(PeripherySPIKey)
val spis = spiParams map { params =>
val spi = LazyModule(new TLSPI(peripheryBusBytes, params))
spi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := spi.intnode
val spi = LazyModule(new TLSPI(pbus.beatBytes, params))
spi.rnode := pbus.toVariableWidthSlaves
ibus.fromSync := spi.intnode
spi
}
}
@ -36,13 +36,13 @@ trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPI
case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
trait HasPeripherySPIFlash extends HasSystemNetworks {
trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
val spiFlashParams = p(PeripherySPIFlashKey)
val qspis = spiFlashParams map { params =>
val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params))
qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
intBus.intnode := qspi.intnode
val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
qspi.rnode := pbus.toVariableWidthSlaves
qspi.fnode := TLFragmenter(1, pbus.blockBytes)(pbus.toFixedWidthSlaves)
ibus.fromSync := qspi.intnode
qspi
}
}
@ -60,4 +60,3 @@ trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeriphe
io <> device.module.io.port
}
}