riscv/sifive-blocks
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Merge remote-tracking branch 'origin/master' into typed_pad_ctrl

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Megan Wachs
2017-07-24 09:17:53 -07:00
parent 2bad829e6e 9ae6413273
commit 0a80d1987d
10 changed files with 71 additions and 76 deletions
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23
src/main/scala/devices/mockaon/MockAONPeriphery.scala
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@ -3,22 +3,25 @@ package sifive.blocks.devices.mockaon
import Chisel._
import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.devices.debug.HasPeripheryDebug
import freechips.rocketchip.devices.tilelink.HasPeripheryClint
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import freechips.rocketchip.chip.{HasSystemNetworks, HasCoreplexRISCVPlatform}
import freechips.rocketchip.tilelink.{IntXing, TLAsyncCrossingSource, TLFragmenter}
import freechips.rocketchip.tilelink.{IntXing, TLAsyncCrossingSource}
import freechips.rocketchip.util.ResetCatchAndSync
case object PeripheryMockAONKey extends Field[MockAONParams]
trait HasPeripheryMockAON extends HasSystemNetworks with HasCoreplexRISCVPlatform {
trait HasPeripheryMockAON extends HasPeripheryBus
with HasInterruptBus
with HasPeripheryClint
with HasPeripheryDebug {
// We override the clock & Reset here so that all synchronizers, etc
// are in the proper clock domain.
val mockAONParams= p(PeripheryMockAONKey)
val aon = LazyModule(new MockAONWrapper(peripheryBusBytes, mockAONParams))
val aon_int = LazyModule(new IntXing)
aon.node := TLAsyncCrossingSource()(TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node))
aon_int.intnode := aon.intnode
intBus.intnode := aon_int.intnode
val aon = LazyModule(new MockAONWrapper(pbus.beatBytes, mockAONParams))
aon.node := pbus.toAsyncVariableWidthSlaves(sync = 3)
ibus.fromAsync := aon.intnode
}
trait HasPeripheryMockAONBundle {
@ -39,7 +42,7 @@ trait HasPeripheryMockAONModuleImp extends LazyMultiIOModuleImp with HasPeripher
outer.aon.module.clock := Bool(false).asClock
outer.aon.module.reset := Bool(true)
outer.coreplex.module.io.rtcToggle := outer.aon.module.io.rtc.asUInt.toBool
outer.clint.module.io.rtcTick := outer.aon.module.io.rtc.asUInt.toBool
outer.aon.module.io.ndreset := outer.coreplex.module.io.ndreset
outer.aon.module.io.ndreset := outer.debug.module.io.ctrl.ndreset
}