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Merge pull request #2 from sifive/homogenous_bag_peripherals

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Use HeterogenousBag to handle lists of peripherals
This commit is contained in:
Megan Wachs 2017-02-16 18:45:48 -08:00 committed by GitHub
commit 072d0c1b58
4 changed files with 7 additions and 27 deletions
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10
src/main/scala/devices/pwm/PWM.scala
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@ -44,16 +44,6 @@ case class PWMConfig(
regBytes: Int = 4,
ncmp: Int = 4,
cmpWidth: Int = 16)
{
val bc = new PWMBundleConfig(ncmp)
}
case class PWMBundleConfig(
ncmp: Int)
{
def union(that: PWMBundleConfig): PWMBundleConfig =
PWMBundleConfig(scala.math.max(ncmp, that.ncmp))
}
trait HasPWMParameters {
implicit val p: Parameters

10
src/main/scala/devices/pwm/PWMPeriphery.scala
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@ -6,19 +6,20 @@ import config._
import diplomacy.LazyModule
import rocketchip.{TopNetwork,TopNetworkModule}
import uncore.tilelink2.TLFragmenter
import util.HeterogeneousBag
import sifive.blocks.devices.gpio._
class PWMPortIO(c: PWMBundleConfig)(implicit p: Parameters) extends Bundle {
class PWMPortIO(c: PWMConfig)(implicit p: Parameters) extends Bundle {
val port = Vec(c.ncmp, Bool()).asOutput
override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
}
class PWMPinsIO(c: PWMBundleConfig)(implicit p: Parameters) extends Bundle {
class PWMPinsIO(c: PWMConfig)(implicit p: Parameters) extends Bundle {
val pwm = Vec(c.ncmp, new GPIOPin)
}
class PWMGPIOPort(c: PWMBundleConfig)(implicit p: Parameters) extends Module {
class PWMGPIOPort(c: PWMConfig)(implicit p: Parameters) extends Module {
val io = new Bundle {
val pwm = new PWMPortIO(c).flip()
val pins = new PWMPinsIO(c)
@ -43,8 +44,7 @@ trait PeripheryPWMBundle {
val p: Parameters
val pwmConfigs: Seq[PWMConfig]
} =>
val pwm_bc = pwmConfigs.map(_.bc).reduce(_.union(_))
val pwms = Vec(pwmConfigs.size, new PWMPortIO(pwm_bc)(p))
val pwms = HeterogeneousBag(pwmConfigs.map(new PWMPortIO(_)(p)))
}
trait PeripheryPWMModule {

4
src/main/scala/devices/spi/SPIPeriphery.scala
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@ -5,6 +5,7 @@ import Chisel._
import diplomacy.LazyModule
import uncore.tilelink2._
import rocketchip.{TopNetwork,TopNetworkModule}
import util.HeterogeneousBag
trait PeripherySPI {
this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
@ -18,8 +19,7 @@ trait PeripherySPI {
trait PeripherySPIBundle {
this: { val spiConfigs: Seq[SPIConfig] } =>
val spi_bc = spiConfigs.map(_.bc).reduce(_.union(_))
val spis = Vec(spiConfigs.size, new SPIPortIO(spi_bc.toSPIConfig))
val spis = HeterogeneousBag(spiConfigs.map(new SPIPortIO(_)))
}
trait PeripherySPIModule {

10
src/main/scala/devices/spi/TLSPI.scala
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@ -30,7 +30,6 @@ trait SPIConfigBase {
lazy val txDepthBits = log2Floor(txDepth) + 1
lazy val rxDepthBits = log2Floor(rxDepth) + 1
lazy val bc = new SPIBundleConfig(csWidth)
}
case class SPIConfig(
@ -49,15 +48,6 @@ case class SPIConfig(
require(sampleDelay >= 0)
}
case class SPIBundleConfig(csWidth: Int)
{
def union(that: SPIBundleConfig): SPIBundleConfig =
SPIBundleConfig(scala.math.max(csWidth, that.csWidth))
def toSPIConfig: SPIConfig = new SPIConfig(rAddress = -1,
csWidth = csWidth)
}
class SPITopBundle(val i: Vec[Vec[Bool]], val r: Vec[TLBundle]) extends Bundle
class SPITopModule[B <: SPITopBundle](c: SPIConfigBase, bundle: => B, outer: TLSPIBase)