Add missing cloneType methods to pin bundles
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@ -12,6 +12,9 @@ class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
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val scl: T = pingen()
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val sda: T = pingen()
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override def cloneType: this.type =
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this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
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def fromI2CPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
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withClockAndReset(clock, reset) {
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scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
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@ -18,6 +18,9 @@ class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle {
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val pwm: Vec[T] = Vec(c.ncmp, pingen())
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override def cloneType: this.type =
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this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
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def fromPWMPort(port: PWMPortIO) {
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(pwm zip port.port) foreach {case (pin, port) =>
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pin.outputPin(port)
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@ -7,9 +7,12 @@ import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
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class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
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val sck: T = pingen()
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val dq: Vec[T] = Vec(4, pingen())
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val cs: Vec[T] = Vec(c.csWidth, pingen())
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val sck = pingen()
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val dq = Vec(4, pingen())
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val cs = Vec(c.csWidth, pingen())
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override def cloneType: this.type =
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this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
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def fromSPIPort(spi: SPIPortIO, clock: Clock, reset: Bool,
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syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
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@ -44,6 +44,9 @@ class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
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val rxd = pingen()
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val txd = pingen()
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override def cloneType: this.type =
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this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
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def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
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withClockAndReset(clock, reset) {
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txd.outputPin(uart.txd)
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