30 lines
920 B
Scala
30 lines
920 B
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.i2c
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import Chisel._
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import chisel3.experimental.{withClockAndReset}
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import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
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import sifive.blocks.util.ShiftRegisterInit
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class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
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val scl: T = pingen()
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val sda: T = pingen()
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override def cloneType: this.type =
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this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
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def fromI2CPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
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withClockAndReset(clock, reset) {
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scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
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scl.o.oe := i2c.scl.oe
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i2c.scl.in := ShiftRegisterInit(scl.i.ival, syncStages, Bool(true))
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sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
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sda.o.oe := i2c.sda.oe
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i2c.sda.in := ShiftRegisterInit(sda.i.ival, syncStages, Bool(true))
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}
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}
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}
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