Add missing cloneType methods to pin bundles
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		| @@ -12,6 +12,9 @@ class I2CPins[T <: Pin](pingen: () => T) extends Bundle { | |||||||
|   val scl: T = pingen() |   val scl: T = pingen() | ||||||
|   val sda: T = pingen() |   val sda: T = pingen() | ||||||
|  |  | ||||||
|  |   override def cloneType: this.type = | ||||||
|  |     this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type] | ||||||
|  |  | ||||||
|   def fromI2CPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = { |   def fromI2CPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = { | ||||||
|     withClockAndReset(clock, reset) { |     withClockAndReset(clock, reset) { | ||||||
|       scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B) |       scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B) | ||||||
|   | |||||||
| @@ -18,6 +18,9 @@ class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle { | |||||||
|  |  | ||||||
|   val pwm: Vec[T] = Vec(c.ncmp, pingen()) |   val pwm: Vec[T] = Vec(c.ncmp, pingen()) | ||||||
|  |  | ||||||
|  |   override def cloneType: this.type = | ||||||
|  |     this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type] | ||||||
|  |  | ||||||
|   def fromPWMPort(port: PWMPortIO) { |   def fromPWMPort(port: PWMPortIO) { | ||||||
|     (pwm zip port.port)  foreach {case (pin, port) => |     (pwm zip port.port)  foreach {case (pin, port) => | ||||||
|       pin.outputPin(port) |       pin.outputPin(port) | ||||||
|   | |||||||
| @@ -7,9 +7,12 @@ import sifive.blocks.devices.pinctrl.{PinCtrl, Pin} | |||||||
|  |  | ||||||
| class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) { | class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) { | ||||||
|  |  | ||||||
|   val sck: T      = pingen() |   val sck = pingen() | ||||||
|   val dq: Vec[T]  = Vec(4, pingen()) |   val dq  = Vec(4, pingen()) | ||||||
|   val cs: Vec[T]  = Vec(c.csWidth, pingen()) |   val cs  = Vec(c.csWidth, pingen()) | ||||||
|  |  | ||||||
|  |   override def cloneType: this.type = | ||||||
|  |     this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type] | ||||||
|  |  | ||||||
|   def fromSPIPort(spi: SPIPortIO, clock: Clock, reset: Bool, |   def fromSPIPort(spi: SPIPortIO, clock: Clock, reset: Bool, | ||||||
|     syncStages: Int = 0, driveStrength: Bool = Bool(false)) { |     syncStages: Int = 0, driveStrength: Bool = Bool(false)) { | ||||||
|   | |||||||
| @@ -44,6 +44,9 @@ class UARTPins[T <: Pin] (pingen: () => T) extends Bundle { | |||||||
|   val rxd = pingen() |   val rxd = pingen() | ||||||
|   val txd = pingen() |   val txd = pingen() | ||||||
|  |  | ||||||
|  |   override def cloneType: this.type = | ||||||
|  |     this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type] | ||||||
|  |  | ||||||
|   def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) { |   def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) { | ||||||
|     withClockAndReset(clock, reset) { |     withClockAndReset(clock, reset) { | ||||||
|       txd.outputPin(uart.txd) |       txd.outputPin(uart.txd) | ||||||
|   | |||||||
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