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xilinx pcie: add the high PCIe address bits (physical path)

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The format is taken from here:
http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
This commit is contained in:
Wesley W. Terpstra
2017-03-02 21:22:41 -08:00
parent 64bff44462
commit 062203ae18
1 changed files with 1 additions and 1 deletions
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src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
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@@ -182,7 +182,7 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
"interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt),
"interrupt-map" -> Seq(1, 2, 3, 4).flatMap(ofMap),
"ranges" -> resources("ranges").map { case Binding(_, ResourceAddress(address, _, _, _)) =>
ResourceMapping(address, 0) },
ResourceMapping(address, BigInt(0x02000000) << 64) },
"interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map(
"interrupt-controller" -> Nil,
"#address-cells" -> ofInt(0),