riscv/sifive-blocks
1
0
Fork 0
Code Releases Activity

allow bundle content params to be specified via a def (#29)

Browse Source
This commit is contained in:
Henry Cook 2017-08-02 11:46:27 -07:00 committed by GitHub
parent fced2323bd
commit 015f87ec6b
3 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/devices/gpio/GPIO.scala
View File

@ -82,7 +82,7 @@ class GPIOPortIO(c: GPIOParams) extends GenericParameterizedBundle(c) {
// It would be better if the IOF were here and // It would be better if the IOF were here and
// we could do the pinmux inside. // we could do the pinmux inside.
trait HasGPIOBundleContents extends Bundle { trait HasGPIOBundleContents extends Bundle {
val params: GPIOParams def params: GPIOParams
val port = new GPIOPortIO(params) val port = new GPIOPortIO(params)
} }

2
src/main/scala/devices/pwm/PWM.scala
View File

@ -44,7 +44,7 @@ case class PWMParams(
cmpWidth: Int = 16) cmpWidth: Int = 16)
trait HasPWMBundleContents extends Bundle { trait HasPWMBundleContents extends Bundle {
val params: PWMParams def params: PWMParams
val gpio = Vec(params.ncmp, Bool()).asOutput val gpio = Vec(params.ncmp, Bool()).asOutput
} }

6
src/main/scala/devices/uart/UARTPeriphery.scala
View File

@ -12,10 +12,10 @@ import sifive.blocks.util.ShiftRegisterInit
case object PeripheryUARTKey extends Field[Seq[UARTParams]] case object PeripheryUARTKey extends Field[Seq[UARTParams]]
trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus { trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
val uartParams = p(PeripheryUARTKey) private val divinit = (p(PeripheryBusParams).frequency / 115200).toInt
val divinit = (p(PeripheryBusParams).frequency / 115200).toInt val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit))
val uarts = uartParams map { params => val uarts = uartParams map { params =>
val uart = LazyModule(new TLUART(pbus.beatBytes, params.copy(divisorInit = divinit))) val uart = LazyModule(new TLUART(pbus.beatBytes, params))
uart.node := pbus.toVariableWidthSlaves uart.node := pbus.toVariableWidthSlaves
ibus.fromSync := uart.intnode ibus.fromSync := uart.intnode
uart uart