Import sd breakout board
This commit is contained in:
commit
9d36d30fe7
24
.gitignore
vendored
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24
.gitignore
vendored
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@ -0,0 +1,24 @@
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||||
# For PCBs designed using KiCad: http://www.kicad-pcb.org/
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# Temporary files
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*.000
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*.bak
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*.bck
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*.kicad_pcb-bak
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||||
*~
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||||
_autosave-*
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*.tmp
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# Netlist files (exported from Eeschema)
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*.net
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# Autorouter files (exported from Pcbnew)
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*.dsn
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*.ses
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# Exported BOM files
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*.xml
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*.csv
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||||
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# Plots
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*.pdf
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61
sd_breakout-cache.lib
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61
sd_breakout-cache.lib
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EESchema-LIBRARY Version 2.3
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#encoding utf-8
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#
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# CONN_01X04
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#
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DEF CONN_01X04 P 0 40 Y N 1 F N
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F0 "P" 0 250 50 H V C CNN
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F1 "CONN_01X04" 100 0 50 V V C CNN
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F2 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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Pin_Header_Straight_1X04
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Pin_Header_Angled_1X04
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Socket_Strip_Straight_1X04
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Socket_Strip_Angled_1X04
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$ENDFPLIST
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DRAW
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S -50 -145 10 -155 0 1 0 N
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S -50 -45 10 -55 0 1 0 N
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S -50 55 10 45 0 1 0 N
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S -50 155 10 145 0 1 0 N
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S -50 200 50 -200 0 1 0 N
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X P1 1 -200 150 150 R 50 50 1 1 P
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X P2 2 -200 50 150 R 50 50 1 1 P
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X P3 3 -200 -50 150 R 50 50 1 1 P
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X P4 4 -200 -150 150 R 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# microSD
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#
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DEF microSD U 0 40 Y Y 1 F N
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F0 "U" 25 -500 60 H V C CNN
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F1 "microSD" 0 500 60 H V C CNN
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F2 "" -50 25 60 H V C CNN
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F3 "" -50 25 60 H V C CNN
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DRAW
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T 0 275 -25 157 0 0 0 µSD Normal 1 C C
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P 2 0 1 39 -135 -125 -65 -125 N
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P 2 0 1 39 -135 -25 -65 -25 N
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P 2 0 1 39 -125 -225 -75 -225 N
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P 2 0 1 39 -125 -175 -75 -175 N
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P 2 0 1 39 -125 -75 -75 -75 N
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P 2 0 1 39 -125 25 -75 25 N
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P 2 0 1 39 -125 75 -75 75 N
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P 2 0 1 39 -125 125 -75 125 N
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P 11 0 1 0 -175 175 0 175 100 275 225 275 225 225 300 225 350 275 600 275 600 -275 -175 -275 -175 175 N
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P 12 0 1 0 -500 425 -100 425 500 425 500 275 600 275 600 -275 500 -275 500 -425 -50 -425 -500 -425 -500 0 -500 425 N
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X DAT2 1 -700 350 200 R 50 50 1 1 I
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X CD/DAT3 2 -700 250 200 R 50 50 1 1 I
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X CMD 3 -700 150 200 R 50 50 1 1 I
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X VDD 4 -700 50 200 R 50 50 1 1 I
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X CLK 5 -700 -50 200 R 50 50 1 1 I
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X GND 6 -700 -150 200 R 50 50 1 1 I
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X DAT0 7 -700 -250 200 R 50 50 1 1 I
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X DAT1 8 -700 -350 200 R 50 50 1 1 I
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X Shield ~ 700 -350 200 L 50 50 1 1 I
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ENDDRAW
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ENDDEF
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#
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#End Library
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345
sd_breakout.kicad_pcb
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345
sd_breakout.kicad_pcb
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@ -0,0 +1,345 @@
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(kicad_pcb (version 4) (host pcbnew 4.0.2+dfsg1-stable)
|
||||
|
||||
(general
|
||||
(links 12)
|
||||
(no_connects 0)
|
||||
(area 145.974999 86.331666 184.679001 114.328333)
|
||||
(thickness 1.6)
|
||||
(drawings 4)
|
||||
(tracks 26)
|
||||
(zones 0)
|
||||
(modules 3)
|
||||
(nets 9)
|
||||
)
|
||||
|
||||
(page A4)
|
||||
(layers
|
||||
(0 F.Cu signal)
|
||||
(31 B.Cu signal hide)
|
||||
(32 B.Adhes user)
|
||||
(33 F.Adhes user)
|
||||
(34 B.Paste user)
|
||||
(35 F.Paste user)
|
||||
(36 B.SilkS user)
|
||||
(37 F.SilkS user)
|
||||
(38 B.Mask user)
|
||||
(39 F.Mask user)
|
||||
(40 Dwgs.User user)
|
||||
(41 Cmts.User user)
|
||||
(42 Eco1.User user)
|
||||
(43 Eco2.User user)
|
||||
(44 Edge.Cuts user)
|
||||
(45 Margin user)
|
||||
(46 B.CrtYd user)
|
||||
(47 F.CrtYd user)
|
||||
(48 B.Fab user)
|
||||
(49 F.Fab user)
|
||||
)
|
||||
|
||||
(setup
|
||||
(last_trace_width 0.35)
|
||||
(trace_clearance 0.2)
|
||||
(zone_clearance 0.508)
|
||||
(zone_45_only no)
|
||||
(trace_min 0.2)
|
||||
(segment_width 0.2)
|
||||
(edge_width 0.15)
|
||||
(via_size 0.6)
|
||||
(via_drill 0.4)
|
||||
(via_min_size 0.4)
|
||||
(via_min_drill 0.3)
|
||||
(uvia_size 0.3)
|
||||
(uvia_drill 0.1)
|
||||
(uvias_allowed no)
|
||||
(uvia_min_size 0.2)
|
||||
(uvia_min_drill 0.1)
|
||||
(pcb_text_width 0.3)
|
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(pcb_text_size 1.5 1.5)
|
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(mod_edge_width 0.15)
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(mod_text_size 1 1)
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(mod_text_width 0.15)
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(pad_size 2.032 1.7272)
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(pad_drill 1.016)
|
||||
(pad_to_mask_clearance 0.2)
|
||||
(aux_axis_origin 0 0)
|
||||
(visible_elements FFFFFF7F)
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||||
(pcbplotparams
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(layerselection 0x00000_00000001)
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(usegerberextensions false)
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||||
(excludeedgelayer true)
|
||||
(linewidth 0.100000)
|
||||
(plotframeref false)
|
||||
(viasonmask false)
|
||||
(mode 1)
|
||||
(useauxorigin false)
|
||||
(hpglpennumber 1)
|
||||
(hpglpenspeed 20)
|
||||
(hpglpendiameter 15)
|
||||
(hpglpenoverlay 2)
|
||||
(psnegative false)
|
||||
(psa4output false)
|
||||
(plotreference true)
|
||||
(plotvalue true)
|
||||
(plotinvisibletext false)
|
||||
(padsonsilk false)
|
||||
(subtractmaskfromsilk false)
|
||||
(outputformat 4)
|
||||
(mirror true)
|
||||
(drillshape 1)
|
||||
(scaleselection 1)
|
||||
(outputdirectory ""))
|
||||
)
|
||||
|
||||
(net 0 "")
|
||||
(net 1 "Net-(P1-Pad1)")
|
||||
(net 2 "Net-(P1-Pad2)")
|
||||
(net 3 "Net-(P1-Pad3)")
|
||||
(net 4 "Net-(P1-Pad4)")
|
||||
(net 5 "Net-(P2-Pad1)")
|
||||
(net 6 "Net-(P2-Pad2)")
|
||||
(net 7 "Net-(P2-Pad3)")
|
||||
(net 8 "Net-(P2-Pad4)")
|
||||
|
||||
(net_class Default "This is the default net class."
|
||||
(clearance 0.2)
|
||||
(trace_width 0.35)
|
||||
(via_dia 0.6)
|
||||
(via_drill 0.4)
|
||||
(uvia_dia 0.3)
|
||||
(uvia_drill 0.1)
|
||||
(add_net "Net-(P1-Pad1)")
|
||||
(add_net "Net-(P1-Pad2)")
|
||||
(add_net "Net-(P1-Pad3)")
|
||||
(add_net "Net-(P1-Pad4)")
|
||||
(add_net "Net-(P2-Pad1)")
|
||||
(add_net "Net-(P2-Pad2)")
|
||||
(add_net "Net-(P2-Pad3)")
|
||||
(add_net "Net-(P2-Pad4)")
|
||||
)
|
||||
|
||||
(module Pin_Headers:Pin_Header_Straight_1x04 (layer B.Cu) (tedit 5AEB2850) (tstamp 5AEB2723)
|
||||
(at 160.02 91.44 90)
|
||||
(descr "Through hole pin header")
|
||||
(tags "pin header")
|
||||
(path /5AEB264D)
|
||||
(fp_text reference P1 (at 0 5.1 90) (layer B.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
|
||||
)
|
||||
(fp_text value CONN_01X04 (at 0 3.1 90) (layer B.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
|
||||
)
|
||||
(fp_line (start -1.75 1.75) (end -1.75 -9.4) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start 1.75 1.75) (end 1.75 -9.4) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.75 1.75) (end 1.75 1.75) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.75 -9.4) (end 1.75 -9.4) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.27 -1.27) (end -1.27 -8.89) (layer B.SilkS) (width 0.15))
|
||||
(fp_line (start 1.27 -1.27) (end 1.27 -8.89) (layer B.SilkS) (width 0.15))
|
||||
(fp_line (start 1.55 1.55) (end 1.55 0) (layer B.SilkS) (width 0.15))
|
||||
(fp_line (start -1.27 -8.89) (end 1.27 -8.89) (layer B.SilkS) (width 0.15))
|
||||
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer B.SilkS) (width 0.15))
|
||||
(fp_line (start -1.55 0) (end -1.55 1.55) (layer B.SilkS) (width 0.15))
|
||||
(fp_line (start -1.55 1.55) (end 1.55 1.55) (layer B.SilkS) (width 0.15))
|
||||
(pad 1 thru_hole oval (at 0 0 90) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
|
||||
(net 1 "Net-(P1-Pad1)"))
|
||||
(pad 2 thru_hole oval (at 0 -2.54 90) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
|
||||
(net 2 "Net-(P1-Pad2)"))
|
||||
(pad 3 thru_hole oval (at 0 -5.08 90) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
|
||||
(net 3 "Net-(P1-Pad3)"))
|
||||
(pad 4 thru_hole oval (at 0 -7.62 90) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
|
||||
(net 4 "Net-(P1-Pad4)"))
|
||||
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x04.wrl
|
||||
(at (xyz 0 -0.15 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 90))
|
||||
)
|
||||
)
|
||||
|
||||
(module Pin_Headers:Pin_Header_Straight_1x04 (layer B.Cu) (tedit 5AEB2846) (tstamp 5AEB272B)
|
||||
(at 152.4 109.22 270)
|
||||
(descr "Through hole pin header")
|
||||
(tags "pin header")
|
||||
(path /5AEB2698)
|
||||
(fp_text reference P2 (at 0 5.1 270) (layer B.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
|
||||
)
|
||||
(fp_text value CONN_01X04 (at 0 3.1 270) (layer B.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
|
||||
)
|
||||
(fp_line (start -1.75 1.75) (end -1.75 -9.4) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start 1.75 1.75) (end 1.75 -9.4) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.75 1.75) (end 1.75 1.75) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.75 -9.4) (end 1.75 -9.4) (layer B.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.27 -1.27) (end -1.27 -8.89) (layer B.SilkS) (width 0.15))
|
||||
(fp_line (start 1.27 -1.27) (end 1.27 -8.89) (layer B.SilkS) (width 0.15))
|
||||
(fp_line (start 1.55 1.55) (end 1.55 0) (layer B.SilkS) (width 0.15))
|
||||
(fp_line (start -1.27 -8.89) (end 1.27 -8.89) (layer B.SilkS) (width 0.15))
|
||||
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer B.SilkS) (width 0.15))
|
||||
(fp_line (start -1.55 0) (end -1.55 1.55) (layer B.SilkS) (width 0.15))
|
||||
(fp_line (start -1.55 1.55) (end 1.55 1.55) (layer B.SilkS) (width 0.15))
|
||||
(pad 1 thru_hole oval (at 0 0 270) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
|
||||
(net 5 "Net-(P2-Pad1)"))
|
||||
(pad 2 thru_hole rect (at 0 -2.54 270) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
|
||||
(net 6 "Net-(P2-Pad2)"))
|
||||
(pad 3 thru_hole oval (at 0 -5.08 270) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
|
||||
(net 7 "Net-(P2-Pad3)"))
|
||||
(pad 4 thru_hole oval (at 0 -7.62 270) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
|
||||
(net 8 "Net-(P2-Pad4)"))
|
||||
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x04.wrl
|
||||
(at (xyz 0 -0.15 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 90))
|
||||
)
|
||||
)
|
||||
|
||||
(module footprints:microSDSpring (layer F.Cu) (tedit 5AEB23DD) (tstamp 5AEB273B)
|
||||
(at 147.828 105.873)
|
||||
(path /5AEB28C2)
|
||||
(fp_text reference U1 (at 7.112 0) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value microSD (at 6.604 -11.176) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start 16.764 -10.668) (end 15.748 -10.668) (layer F.SilkS) (width 0.15))
|
||||
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|
||||
(fp_line (start 16.764 -12.7) (end 16.764 -10.668) (layer F.SilkS) (width 0.15))
|
||||
(fp_arc (start 36.576 -4.572) (end 15.748 1.524) (angle 32.62770306) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 0.508 1.524) (end 15.748 1.524) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 0.508 -12.7) (end 0.508 1.524) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 16.256 -12.7) (end 0.508 -12.7) (layer F.SilkS) (width 0.15))
|
||||
(pad 6 smd rect (at 0.7 -0.875) (size 1.4 1.75) (layers F.Cu F.Paste F.Mask)
|
||||
(net 6 "Net-(P2-Pad2)"))
|
||||
(pad 6 smd rect (at 0.7 -6.675) (size 1.4 1.75) (layers F.Cu F.Paste F.Mask)
|
||||
(net 6 "Net-(P2-Pad2)"))
|
||||
(pad 6 smd rect (at 15.075 0.7 90) (size 1.4 1.75) (layers F.Cu F.Paste F.Mask)
|
||||
(net 6 "Net-(P2-Pad2)"))
|
||||
(pad 6 smd rect (at 15.95 -12.4 90) (size 1.4 1.75) (layers F.Cu F.Paste F.Mask)
|
||||
(net 6 "Net-(P2-Pad2)"))
|
||||
(pad 8 smd rect (at 12.45 0 180) (size 1.5 0.7) (layers F.Cu F.Paste F.Mask)
|
||||
(net 8 "Net-(P2-Pad4)") (solder_mask_margin 0.1) (clearance 0.05))
|
||||
(pad 7 smd rect (at 12.45 -1.1 180) (size 1.5 0.7) (layers F.Cu F.Paste F.Mask)
|
||||
(net 7 "Net-(P2-Pad3)") (solder_mask_margin 0.1) (clearance 0.1))
|
||||
(pad 6 smd rect (at 12.446 -2.2 180) (size 1.5 0.7) (layers F.Cu F.Paste F.Mask)
|
||||
(net 6 "Net-(P2-Pad2)") (solder_mask_margin 0.1) (clearance 0.1))
|
||||
(pad 5 smd rect (at 12.446 -3.3 180) (size 1.5 0.7) (layers F.Cu F.Paste F.Mask)
|
||||
(net 5 "Net-(P2-Pad1)") (solder_mask_margin 0.1) (clearance 0.1))
|
||||
(pad 4 smd rect (at 12.446 -4.4 180) (size 1.5 0.7) (layers F.Cu F.Paste F.Mask)
|
||||
(net 4 "Net-(P1-Pad4)") (solder_mask_margin 0.1) (clearance 0.1))
|
||||
(pad 3 smd rect (at 12.446 -5.5 180) (size 1.5 0.7) (layers F.Cu F.Paste F.Mask)
|
||||
(net 3 "Net-(P1-Pad3)") (solder_mask_margin 0.1) (clearance 0.1))
|
||||
(pad 2 smd rect (at 12.446 -6.6 180) (size 1.5 0.7) (layers F.Cu F.Paste F.Mask)
|
||||
(net 2 "Net-(P1-Pad2)") (solder_mask_margin 0.1) (clearance 0.1))
|
||||
(pad 1 smd rect (at 12.446 -7.7 180) (size 1.5 0.7) (layers F.Cu F.Paste F.Mask)
|
||||
(net 1 "Net-(P1-Pad1)") (solder_mask_margin 0.1) (clearance 0.1))
|
||||
)
|
||||
|
||||
(gr_line (start 146.05 112.395) (end 146.05 88.265) (layer Edge.Cuts) (width 0.15))
|
||||
(gr_line (start 166.37 112.395) (end 146.05 112.395) (layer Edge.Cuts) (width 0.15))
|
||||
(gr_line (start 166.37 88.265) (end 166.37 112.395) (layer Edge.Cuts) (width 0.15))
|
||||
(gr_line (start 146.05 88.265) (end 166.37 88.265) (layer Edge.Cuts) (width 0.15))
|
||||
|
||||
(segment (start 160.274 98.173) (end 160.274 91.694) (width 0.35) (layer F.Cu) (net 1))
|
||||
(segment (start 160.274 91.694) (end 160.02 91.44) (width 0.25) (layer F.Cu) (net 1))
|
||||
(segment (start 160.274 99.273) (end 159.274 99.273) (width 0.35) (layer F.Cu) (net 2))
|
||||
(segment (start 157.48 92.706) (end 157.48 91.44) (width 0.35) (layer F.Cu) (net 2))
|
||||
(segment (start 157.48 97.479) (end 157.48 92.706) (width 0.35) (layer F.Cu) (net 2))
|
||||
(segment (start 159.274 99.273) (end 157.48 97.479) (width 0.35) (layer F.Cu) (net 2))
|
||||
(segment (start 160.274 100.373) (end 159.274 100.373) (width 0.35) (layer F.Cu) (net 3))
|
||||
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(segment (start 159.274 101.473) (end 152.4 94.599) (width 0.35) (layer F.Cu) (net 4))
|
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|
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|
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|
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|
||||
(segment (start 157.48 107.954) (end 157.48 109.22) (width 0.35) (layer F.Cu) (net 7))
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(segment (start 157.48 106.571) (end 157.48 107.954) (width 0.35) (layer F.Cu) (net 7))
|
||||
(segment (start 159.278 104.773) (end 157.48 106.571) (width 0.35) (layer F.Cu) (net 7))
|
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|
||||
(segment (start 160.278 108.962) (end 160.02 109.22) (width 0.25) (layer F.Cu) (net 8))
|
||||
|
||||
(zone (net 6) (net_name "Net-(P2-Pad2)") (layer F.Cu) (tstamp 0) (hatch edge 0.508)
|
||||
(connect_pads (clearance 0.508))
|
||||
(min_thickness 0.254)
|
||||
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
|
||||
(polygon
|
||||
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)
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)
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||||
61
sd_breakout.pro
Normal file
61
sd_breakout.pro
Normal file
@ -0,0 +1,61 @@
|
||||
update=Do 03 Mai 2018 15:59:40 CEST
|
||||
version=1
|
||||
last_client=kicad
|
||||
[pcbnew]
|
||||
version=1
|
||||
LastNetListRead=
|
||||
UseCmpFile=1
|
||||
PadDrill=0.600000000000
|
||||
PadDrillOvalY=0.600000000000
|
||||
PadSizeH=1.500000000000
|
||||
PadSizeV=1.500000000000
|
||||
PcbTextSizeV=1.500000000000
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||||
PcbTextSizeH=1.500000000000
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||||
PcbTextThickness=0.300000000000
|
||||
ModuleTextSizeV=1.000000000000
|
||||
ModuleTextSizeH=1.000000000000
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ModuleTextSizeThickness=0.150000000000
|
||||
SolderMaskClearance=0.000000000000
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||||
SolderMaskMinWidth=0.000000000000
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||||
DrawSegmentWidth=0.200000000000
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BoardOutlineThickness=0.100000000000
|
||||
ModuleOutlineThickness=0.150000000000
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[general]
|
||||
version=1
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
LibName1=power
|
||||
LibName2=device
|
||||
LibName3=transistors
|
||||
LibName4=conn
|
||||
LibName5=linear
|
||||
LibName6=regul
|
||||
LibName7=74xx
|
||||
LibName8=cmos4000
|
||||
LibName9=adc-dac
|
||||
LibName10=memory
|
||||
LibName11=xilinx
|
||||
LibName12=microcontrollers
|
||||
LibName13=dsp
|
||||
LibName14=microchip
|
||||
LibName15=analog_switches
|
||||
LibName16=motorola
|
||||
LibName17=texas
|
||||
LibName18=intel
|
||||
LibName19=audio
|
||||
LibName20=interface
|
||||
LibName21=digital-audio
|
||||
LibName22=philips
|
||||
LibName23=display
|
||||
LibName24=cypress
|
||||
LibName25=siliconi
|
||||
LibName26=opto
|
||||
LibName27=atmel
|
||||
LibName28=contrib
|
||||
LibName29=valves
|
||||
LibName30=/u/mai11bqv/repos/kicad_libs/symbols/microSD
|
||||
105
sd_breakout.sch
Normal file
105
sd_breakout.sch
Normal file
@ -0,0 +1,105 @@
|
||||
EESchema Schematic File Version 2
|
||||
LIBS:power
|
||||
LIBS:device
|
||||
LIBS:transistors
|
||||
LIBS:conn
|
||||
LIBS:linear
|
||||
LIBS:regul
|
||||
LIBS:74xx
|
||||
LIBS:cmos4000
|
||||
LIBS:adc-dac
|
||||
LIBS:memory
|
||||
LIBS:xilinx
|
||||
LIBS:microcontrollers
|
||||
LIBS:dsp
|
||||
LIBS:microchip
|
||||
LIBS:analog_switches
|
||||
LIBS:motorola
|
||||
LIBS:texas
|
||||
LIBS:intel
|
||||
LIBS:audio
|
||||
LIBS:interface
|
||||
LIBS:digital-audio
|
||||
LIBS:philips
|
||||
LIBS:display
|
||||
LIBS:cypress
|
||||
LIBS:siliconi
|
||||
LIBS:opto
|
||||
LIBS:atmel
|
||||
LIBS:contrib
|
||||
LIBS:valves
|
||||
LIBS:microSD
|
||||
LIBS:sd_breakout-cache
|
||||
EELAYER 25 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 1 1
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
Wire Wire Line
|
||||
4150 3150 4350 3150
|
||||
Wire Wire Line
|
||||
4150 3250 4350 3250
|
||||
Wire Wire Line
|
||||
4150 3350 4350 3350
|
||||
Wire Wire Line
|
||||
4150 3450 4350 3450
|
||||
Wire Wire Line
|
||||
4150 3550 4350 3550
|
||||
Wire Wire Line
|
||||
4150 3750 4350 3750
|
||||
Wire Wire Line
|
||||
4150 3850 4350 3850
|
||||
Wire Wire Line
|
||||
4150 3650 4350 3650
|
||||
Wire Wire Line
|
||||
4250 3650 4250 4050
|
||||
Connection ~ 4250 3650
|
||||
Wire Wire Line
|
||||
4250 4050 5800 4050
|
||||
Wire Wire Line
|
||||
5800 4050 5800 3850
|
||||
Wire Wire Line
|
||||
5800 3850 5750 3850
|
||||
$Comp
|
||||
L CONN_01X04 P1
|
||||
U 1 1 5AEB264D
|
||||
P 3950 3300
|
||||
F 0 "P1" H 4100 3300 50 0000 C CNN
|
||||
F 1 "CONN_01X04" V 4050 3300 50 0001 C CNN
|
||||
F 2 "Pin_Headers:Pin_Header_Straight_1x04" H 3950 3300 50 0001 C CNN
|
||||
F 3 "" H 3950 3300 50 0000 C CNN
|
||||
1 3950 3300
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L CONN_01X04 P2
|
||||
U 1 1 5AEB2698
|
||||
P 3950 3700
|
||||
F 0 "P2" H 4100 3700 50 0000 C CNN
|
||||
F 1 "CONN_01X04" V 4050 3700 50 0001 C CNN
|
||||
F 2 "Pin_Headers:Pin_Header_Straight_1x04" H 3950 3700 50 0001 C CNN
|
||||
F 3 "" H 3950 3700 50 0000 C CNN
|
||||
1 3950 3700
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L microSD U1
|
||||
U 1 1 5AEB28C2
|
||||
P 5050 3500
|
||||
F 0 "U1" H 5075 3000 60 0000 C CNN
|
||||
F 1 "microSD" H 5050 4000 60 0000 C CNN
|
||||
F 2 "footprints:microSDSpring" H 5000 3525 60 0001 C CNN
|
||||
F 3 "" H 5000 3525 60 0000 C CNN
|
||||
1 5050 3500
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$EndSCHEMATC
|
||||
Loading…
Reference in New Issue
Block a user