| .. |
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Arbiters.scala
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move junctions utils into top-level utils package
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2016-09-13 20:47:04 -07:00 |
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AsyncQueue.scala
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AsyncQueue: cope with far reset propagation delay
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2016-10-14 18:05:35 -07:00 |
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BlackBoxRegs.scala
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Simplify AsyncResetReg
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2016-10-08 21:29:40 -07:00 |
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ClockDivider.scala
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replace verilog clock divider with one written in Chisel
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2016-09-22 11:32:29 -07:00 |
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ConfigUtils.scala
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make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs
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2016-09-15 13:04:01 -07:00 |
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Counters.scala
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Move a bunch more things into util package
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2016-09-29 14:23:42 -07:00 |
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Crossing.scala
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crossings: use flip not flip()
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2016-10-10 13:13:31 -07:00 |
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GeneratorUtils.scala
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tilelink2: move general-purpose code out of tilelink2 package
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2016-10-03 16:22:28 -07:00 |
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GenericParameterizedBundle.scala
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tilelink2: move general-purpose code out of tilelink2 package
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2016-10-03 16:22:28 -07:00 |
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HellaQueue.scala
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move junctions utils into top-level utils package
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2016-09-13 20:47:04 -07:00 |
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LatencyPipe.scala
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[util] move LatencyPipe into util
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2016-09-15 13:30:34 -07:00 |
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Misc.scala
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don't use Scala to Chisel implicit conversions outside of rocket
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2016-09-29 14:35:42 -07:00 |
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Package.scala
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Fix PopCountAtLeast, un-breaking BTB
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2016-10-07 21:20:40 -07:00 |
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PositionalMultiQueue.scala
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PositionalMultiQueue: work around vcs Lint report
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2016-10-10 11:21:49 -07:00 |
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ReorderQueue.scala
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move junctions utils into top-level utils package
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2016-09-13 20:47:04 -07:00 |
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Timer.scala
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correctly initialize the active flag
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2016-10-03 17:56:30 -07:00 |
