Megan Wachs 9de06f8c83 Merge remote-tracking branch 'origin/master' into debug_v013_pr

2017-03-30 08:01:11 -07:00

..

.gitignore

Write test harness in Chisel

2016-08-15 23:27:27 -07:00

Makefile

Use PROJECT rather than MODEL in name of binary and generated src files.

2016-09-19 13:23:17 -07:00

Makefrag

debug: remove old Verilog DebugTransportModuleJtag file as it has been replaced by Chisel version

2017-03-27 21:24:44 -07:00

Makefrag-verilog

Do allow make to remove .vpd files on Ctrl-C

2017-03-30 00:36:23 -07:00

vlsi_mem_gen

RANDOMIZE_MEM_INIT vlsi_mem_gen (#572)

2017-03-07 01:56:15 -08:00