197 lines
6.8 KiB
Scala
197 lines
6.8 KiB
Scala
// See LICENSE.Berkeley for license details.
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// See LICENSE.SiFive for license details.
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package rocket
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import Chisel._
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import config._
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import diplomacy._
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import tile._
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import uncore.tilelink2._
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import uncore.util.Code
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import util._
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import Chisel.ImplicitConversions._
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case class ICacheParams(
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nSets: Int = 64,
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nWays: Int = 4,
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rowBits: Int = 128,
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nTLBEntries: Int = 32,
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cacheIdBits: Int = 0,
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ecc: Option[Code] = None,
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blockBytes: Int = 64) extends L1CacheParams {
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def replacement = new RandomReplacement(nWays)
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}
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trait HasL1ICacheParameters extends HasL1CacheParameters with HasCoreParameters {
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val cacheParams = tileParams.icache.get
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}
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class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICacheParameters {
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val addr = UInt(width = vaddrBits)
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}
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class ICacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICacheParameters {
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val data = Bits(width = coreInstBits)
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val datablock = Bits(width = rowBits)
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}
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class ICache(val latency: Int)(implicit p: Parameters) extends LazyModule {
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lazy val module = new ICacheModule(this)
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val node = TLClientNode(TLClientParameters(sourceId = IdRange(0,1)))
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}
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class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
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val req = Valid(new ICacheReq).flip
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val s1_paddr = UInt(INPUT, paddrBits) // delayed one cycle w.r.t. req
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val s1_kill = Bool(INPUT) // delayed one cycle w.r.t. req
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val s2_kill = Bool(INPUT) // delayed two cycles; prevents I$ miss emission
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val resp = Valid(UInt(width = coreInstBits * fetchWidth))
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val invalidate = Bool(INPUT)
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val mem = outer.node.bundleOut
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}
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class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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with HasL1ICacheParameters {
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val io = new ICacheBundle(outer)
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val edge = outer.node.edgesOut(0)
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val tl_out = io.mem(0)
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require(isPow2(nSets) && isPow2(nWays))
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require(isPow2(coreInstBytes))
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require(!usingVM || pgIdxBits >= untagBits)
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val s_ready :: s_request :: s_refill :: Nil = Enum(UInt(), 3)
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val state = Reg(init=s_ready)
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val invalidated = Reg(Bool())
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val refill_addr = Reg(UInt(width = paddrBits))
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val s1_tag_hit = Wire(Vec(nWays, Bool()))
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val s1_any_tag_hit = s1_tag_hit.reduce(_||_)
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val s1_valid = Reg(init=Bool(false))
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val out_valid = s1_valid && state === s_ready && !io.s1_kill
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val s1_idx = io.s1_paddr(untagBits-1,blockOffBits)
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val s1_tag = io.s1_paddr(tagBits+untagBits-1,untagBits)
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val s1_hit = out_valid && s1_any_tag_hit
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val s1_miss = s1_valid && state === s_ready && !s1_any_tag_hit
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val s0_valid = io.req.valid && state === s_ready
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val s0_vaddr = io.req.bits.addr
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s1_valid := s0_valid
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when (s1_miss) { refill_addr := io.s1_paddr }
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val refill_tag = refill_addr(tagBits+untagBits-1,untagBits)
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val refill_idx = refill_addr(untagBits-1,blockOffBits)
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val (_, _, refill_done, refill_cnt) = edge.count(tl_out.d)
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tl_out.d.ready := Bool(true)
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require (edge.manager.minLatency > 0)
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val repl_way = if (isDM) UInt(0) else LFSR16(s1_miss)(log2Up(nWays)-1,0)
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val entagbits = code.width(tagBits)
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val tag_array = SeqMem(nSets, Vec(nWays, Bits(width = entagbits)))
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val tag_rdata = tag_array.read(s0_vaddr(untagBits-1,blockOffBits), !refill_done && s0_valid)
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when (refill_done) {
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val tag = code.encode(refill_tag)
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tag_array.write(refill_idx, Vec.fill(nWays)(tag), Vec.tabulate(nWays)(repl_way === _))
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}
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val vb_array = Reg(init=Bits(0, nSets*nWays))
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when (refill_done && !invalidated) {
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vb_array := vb_array.bitSet(Cat(repl_way, refill_idx), Bool(true))
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}
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val invalidate = Wire(init = io.invalidate)
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when (invalidate) {
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vb_array := Bits(0)
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invalidated := Bool(true)
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}
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val s1_tag_disparity = Wire(Vec(nWays, Bool()))
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val wordBits = coreInstBits * fetchWidth
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val s1_dout = Wire(Vec(nWays, UInt(width = code.width(wordBits))))
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val s1_dout_valid = RegNext(s0_valid)
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for (i <- 0 until nWays) {
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val s1_vb = vb_array(Cat(UInt(i), io.s1_paddr(untagBits-1,blockOffBits))).toBool
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s1_tag_disparity(i) := code.decode(tag_rdata(i)).error
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s1_tag_hit(i) := s1_vb && code.decode(tag_rdata(i)).uncorrected === s1_tag
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}
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require(rowBits % wordBits == 0)
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val data_arrays = Seq.fill(rowBits / wordBits) { SeqMem(nSets * refillCycles, Vec(nWays, UInt(width = code.width(wordBits)))) }
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for ((data_array, i) <- data_arrays zipWithIndex) {
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val wen = tl_out.d.valid
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when (wen) {
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val idx = (refill_idx << log2Ceil(refillCycles)) | refill_cnt
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val data = tl_out.d.bits.data(wordBits*(i+1)-1, wordBits*i)
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data_array.write(idx, Vec.fill(nWays)(code.encode(data)), (0 until nWays).map(repl_way === _))
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}
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def wordMatch(addr: UInt) = addr.extract(log2Ceil(rowBytes)-1, log2Ceil(wordBits/8)) === i
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val s0_raddr = s0_vaddr(untagBits-1,blockOffBits-log2Ceil(refillCycles))
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val dout = data_array.read(s0_raddr, !wen && (s0_valid && wordMatch(s0_vaddr)))
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when (wordMatch(io.s1_paddr)) {
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s1_dout := dout
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}
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}
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/*
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for ((data_array, i) <- data_arrays zipWithIndex) {
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val wen = tl_out.d.valid && repl_way === UInt(i)
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when (wen) {
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val e_d = code.encode(tl_out.d.bits.data)
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data_array.write((refill_idx << log2Ceil(refillCycles)) | refill_cnt, e_d)
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}
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val s0_raddr = s0_vaddr(untagBits-1,blockOffBits-log2Ceil(refillCycles))
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s1_dout(i) := data_array.read(s0_raddr, !wen && s0_valid)
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}
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*/
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// output signals
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outer.latency match {
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case 1 =>
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require(code.width(rowBits) == rowBits) // no ECC
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io.resp.bits := Mux1H(s1_tag_hit, s1_dout)
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io.resp.valid := s1_hit
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case 2 =>
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val s2_valid = RegNext(out_valid, Bool(false))
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val s2_hit = RegNext(s1_hit, Bool(false))
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val s2_tag_hit = RegEnable(s1_tag_hit, s1_valid)
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val s2_dout = RegEnable(s1_dout, s1_valid)
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val s2_way_mux = Mux1H(s2_tag_hit, s2_dout)
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val s2_tag_disparity = RegEnable(s1_tag_disparity, s1_valid).asUInt.orR
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val s2_data_disparity = code.decode(s2_way_mux).error
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val s2_disparity = s2_tag_disparity || s2_data_disparity
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when (s2_valid && s2_disparity) { invalidate := true }
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io.resp.bits := code.decode(s2_way_mux).uncorrected
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io.resp.valid := s2_hit && !s2_disparity
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}
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tl_out.a.valid := state === s_request && !io.s2_kill
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tl_out.a.bits := edge.Get(
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fromSource = UInt(0),
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toAddress = (refill_addr >> blockOffBits) << blockOffBits,
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lgSize = lgCacheBlockBytes)._2
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tl_out.b.ready := Bool(true)
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tl_out.c.valid := Bool(false)
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tl_out.e.valid := Bool(false)
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// control state machine
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switch (state) {
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is (s_ready) {
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when (s1_miss && !io.s1_kill) { state := s_request }
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invalidated := Bool(false)
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}
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is (s_request) {
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when (tl_out.a.ready) { state := s_refill }
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when (io.s2_kill) { state := s_ready }
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}
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}
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when (refill_done) {
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assert(state === s_refill)
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state := s_ready
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}
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}
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