ea76800d1a
io.resp.valid could have been valid the cycle after reset, causing the write mask in the acquire tracker to have an erroneous value after reset. This caused the L1 I$ to be refilled with the wrong data. This probably only affects programs loaded with +loadmem and so shouldn't matter for the EOS24 silicon. It should only affect the first L2 xact, which, in practice, would be an HTIF write to load the program. |
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| .. | ||
| project | ||
| src/main/scala | ||
| .gitignore | ||
| build.sbt | ||
| chisel-dependent.sbt | ||
| LICENSE | ||
| README.md | ||
Uncore Library
This is the repository for uncore components assosciated with Rocket chip project. To uses these modules, include this repo as a git submodule within the your chip repository and add it as Project in your chip's build.scala. These components are only dependent on Chisel, i.e.
lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(chisel)
Documentation for the uncore library is available here and an overview of the TileLink Protocol is available here