201 lines
7.1 KiB
Scala
201 lines
7.1 KiB
Scala
package rocket
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import Chisel._
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import Node._;
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import Constants._;
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class ioHost(w: Int, view: List[String] = null) extends Bundle(view)
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{
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val in = new ioDecoupled()(Bits(width = w)).flip
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val out = new ioDecoupled()(Bits(width = w))
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}
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class ioHTIF extends Bundle
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{
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val reset = Bool(INPUT)
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val pcr_wen = Bool(INPUT)
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val pcr_ren = Bool(INPUT)
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val pcr_rdy = Bool(OUTPUT)
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val pcr_addr = Bits(5, INPUT)
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val pcr_wdata = Bits(64, INPUT)
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val pcr_rdata = Bits(64, OUTPUT)
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}
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class rocketHTIF(w: Int, ncores: Int) extends Component
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{
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val io = new Bundle {
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val host = new ioHost(w)
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val cpu = Vec(ncores) { new ioHTIF().flip }
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val mem = new ioTileLink
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}
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val short_request_bits = 64
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val long_request_bits = 576
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require(short_request_bits % w == 0)
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val rx_count_w = 13 + log2up(8) - log2up(w) // data size field is 12 bits
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val rx_count = Reg(resetVal = UFix(0,rx_count_w))
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val rx_shifter = Reg() { Bits(width = short_request_bits) }
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val header = Reg() { Bits() }
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val rx_shifter_in = Cat(io.host.in.bits, rx_shifter(short_request_bits-1,w))
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when (io.host.in.valid && io.host.in.ready) {
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rx_shifter := rx_shifter_in
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rx_count := rx_count + UFix(1)
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when (rx_count === UFix(short_request_bits/w-1)) {
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header := rx_shifter_in
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}
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}
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val rx_count_words = rx_count >> UFix(log2up(short_request_bits/w))
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val packet_ram_wen = rx_count(log2up(short_request_bits/w)-1,0).andR &&
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io.host.in.valid && io.host.in.ready
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val packet_ram = Mem(long_request_bits/short_request_bits-1,
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packet_ram_wen, rx_count_words - UFix(1), rx_shifter_in)
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val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UFix() }
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val cmd = header(3,0)
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val size = header(15,4)
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val seqno = header(23,16)
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val addr = header(63,24).toUFix
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val pcr_addr = addr(19,0)
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val pcr_coreid = addr(39,20)
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val pcr_wdata = packet_ram(UFix(0))
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val nack = Mux(cmd === cmd_readmem || cmd === cmd_writemem, size != UFix((1 << OFFSET_BITS)/8),
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Mux(cmd === cmd_readcr || cmd === cmd_writecr, size != UFix(1),
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Bool(true)))
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val tx_count = Reg(resetVal = UFix(0, log2up(long_request_bits/w+1)))
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val packet_ram_raddr = (tx_count >> UFix(log2up(short_request_bits/w)))
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when (io.host.out.valid && io.host.out.ready) {
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tx_count := tx_count + UFix(1)
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}
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val rx_size = Mux(cmd === cmd_writemem || cmd === cmd_writecr, size, UFix(0))
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val rx_done = rx_count >= UFix(short_request_bits/w) && rx_count_words-UFix(1) === rx_size
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val tx_size = Mux(!nack && cmd === cmd_readmem, UFix((1 << OFFSET_BITS)/8),
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Mux(!nack && cmd === cmd_readcr, UFix(1), UFix(0)))
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val tx_done = packet_ram_raddr - UFix(1) === tx_size
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val mem_acked = Reg(resetVal = Bool(false))
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val mem_gxid = Reg() { Bits() }
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val mem_needs_ack = Reg() { Bool() }
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val mem_nacked = Reg(resetVal = Bool(false))
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when (io.mem.xact_rep.valid) {
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mem_acked := Bool(true)
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mem_gxid := io.mem.xact_rep.bits.global_xact_id
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mem_needs_ack := io.mem.xact_rep.bits.require_ack
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}
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when (io.mem.xact_abort.valid) { mem_nacked := Bool(true) }
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val state_rx :: state_pcr :: state_mem_req :: state_mem_wdata :: state_mem_wresp :: state_mem_rdata :: state_mem_finish :: state_tx :: Nil = Enum(8) { UFix() }
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val state = Reg(resetVal = state_rx)
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when (state === state_rx && rx_done) {
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state := Mux(cmd === cmd_readmem || cmd === cmd_writemem, state_mem_req,
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Mux(cmd === cmd_readcr || cmd === cmd_writecr, state_pcr,
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state_tx))
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}
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val pcr_done = Reg() { Bool() }
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when (state === state_pcr && pcr_done) {
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state := state_tx
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}
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val mem_cnt = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
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when (state === state_mem_req && io.mem.xact_init.ready) {
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state := Mux(cmd === cmd_writemem, state_mem_wdata, state_mem_rdata)
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}
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when (state === state_mem_wdata && io.mem.xact_init_data.ready) {
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when (mem_cnt.andR) {
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state := state_mem_wresp
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}
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mem_cnt := mem_cnt + UFix(1)
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}
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when (state === state_mem_wresp) {
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when (mem_nacked) {
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state := state_mem_req
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mem_nacked := Bool(false)
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}
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when (mem_acked) {
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state := state_mem_finish
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mem_acked := Bool(false)
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}
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}
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when (state === state_mem_rdata) {
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when (mem_nacked) {
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state := state_mem_req
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mem_nacked := Bool(false)
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}
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when (io.mem.xact_rep.valid) {
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when (mem_cnt.andR) {
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state := state_mem_finish
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}
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mem_cnt := mem_cnt + UFix(1)
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}
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mem_acked := Bool(false)
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}
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when (state === state_mem_finish && io.mem.xact_finish.ready) {
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state := state_tx
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}
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when (state === state_tx && tx_done) {
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rx_count := UFix(0)
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tx_count := UFix(0)
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state := state_rx
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}
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var mem_req_data: Bits = null
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for (i <- 0 until MEM_DATA_BITS/short_request_bits) {
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val idx = Cat(mem_cnt, UFix(i, log2up(MEM_DATA_BITS/short_request_bits)))
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packet_ram.write(idx, io.mem.xact_rep.bits.data((i+1)*short_request_bits-1, i*short_request_bits),
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state === state_mem_rdata && io.mem.xact_rep.valid)
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mem_req_data = Cat(packet_ram.read(idx), mem_req_data)
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}
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io.mem.xact_init.valid := state === state_mem_req
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io.mem.xact_init.bits.t_type := Mux(cmd === cmd_writemem, X_INIT_WRITE_UNCACHED, X_INIT_READ_UNCACHED)
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io.mem.xact_init.bits.address := addr >> UFix(OFFSET_BITS-3)
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io.mem.xact_init_data.valid:= state === state_mem_wdata
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io.mem.xact_init_data.bits.data := mem_req_data
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io.mem.xact_finish.valid := (state === state_mem_finish) && mem_needs_ack
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io.mem.xact_finish.bits.global_xact_id := mem_gxid
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pcr_done := Bool(false)
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val pcr_mux = (new Mux1H(ncores)) { Bits(width = 64) }
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for (i <- 0 until ncores) {
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val me = pcr_coreid === UFix(i)
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io.cpu(i).pcr_wen := Reg(state === state_pcr && cmd === cmd_writecr && me, resetVal = Bool(false))
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io.cpu(i).pcr_addr := Reg(pcr_addr)
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io.cpu(i).pcr_wdata := Reg(pcr_wdata)
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val my_reset = Reg(resetVal = Bool(true))
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when (io.cpu(i).pcr_wen && io.cpu(i).pcr_rdy) {
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when (io.cpu(i).pcr_addr === UFix(15)) { my_reset := io.cpu(i).pcr_wdata(0) }
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pcr_done := Bool(true)
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}
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io.cpu(i).reset := my_reset
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io.cpu(i).pcr_ren := Reg(state === state_pcr && cmd === cmd_readcr && me, resetVal = Bool(false))
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val rdata = Reg() { Bits() }
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when (io.cpu(i).pcr_ren && io.cpu(i).pcr_rdy) {
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rdata := io.cpu(i).pcr_rdata
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when (io.cpu(i).pcr_addr === UFix(15)) { rdata := my_reset }
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pcr_done := Bool(true)
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}
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pcr_mux.io.sel(i) := Reg(me)
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pcr_mux.io.in(i) := rdata
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}
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val tx_cmd = Mux(nack, cmd_nack, cmd_ack)
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val tx_cmd_ext = Cat(Bits(0, 4-tx_cmd.getWidth), tx_cmd)
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val tx_size_ext = Cat(Bits(0, 12-tx_size.getWidth), tx_size)
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val tx_header = Cat(addr, seqno, tx_size_ext, tx_cmd_ext)
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val tx_data = Mux(packet_ram_raddr === UFix(0), tx_header,
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Mux(packet_ram_raddr === UFix(1) && cmd === cmd_readcr, pcr_mux.io.out,
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packet_ram(packet_ram_raddr - UFix(1))))
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io.host.in.ready := state === state_rx && !rx_done
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io.host.out.valid := state === state_tx && !tx_done
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io.host.out.bits := tx_data >> Cat(tx_count(log2up(short_request_bits/w)-1,0), Bits(0, log2up(w)))
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}
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