62 lines
1.9 KiB
Scala
62 lines
1.9 KiB
Scala
// See LICENSE for license details.
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package rocket
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import Chisel._
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import uncore._
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import Util._
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case object CoreName extends Field[String]
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case object NDCachePorts extends Field[Int]
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case object NTilePorts extends Field[Int]
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case object NPTWPorts extends Field[Int]
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case object BuildRoCC extends Field[Option[() => RoCC]]
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abstract class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
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val io = new Bundle {
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val tilelink = new HeaderlessTileLinkIO
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val host = new HTIFIO
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}
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}
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class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
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val icache = Module(new Frontend, { case CacheName => "L1I"; case CoreName => "Rocket" })
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val dcache = Module(new HellaCache, { case CacheName => "L1D" })
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val ptw = Module(new PTW(params(NPTWPorts)))
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val core = Module(new Core, { case CoreName => "Rocket" })
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dcache.io.cpu.sret := core.io.dmem.sret
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val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts)))
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dcArb.io.requestor(0) <> ptw.io.mem
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dcArb.io.requestor(1) <> core.io.dmem
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dcArb.io.mem <> dcache.io.cpu
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ptw.io.requestor(0) <> icache.io.ptw
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ptw.io.requestor(1) <> dcache.io.ptw
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core.io.host <> io.host
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core.io.imem <> icache.io.cpu
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core.io.ptw <> ptw.io.dpath
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val memArb = Module(new RocketTileLinkIOArbiter(params(NTilePorts)))
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io.tilelink <> memArb.io.out
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memArb.io.in(0) <> dcache.io.mem
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memArb.io.in(1) <> HeaderlessTileLinkIOWrapper(icache.io.mem)
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//If so specified, build an RoCC module and wire it in
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params(BuildRoCC)
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.map { br => br() }
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.foreach { rocc =>
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val dcIF = Module(new SimpleHellaCacheIF)
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core.io.rocc <> rocc.io
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dcIF.io.requestor <> rocc.io.mem
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dcArb.io.requestor(2) <> dcIF.io.cache
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memArb.io.in(2) <> HeaderlessTileLinkIOWrapper(rocc.io.imem)
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memArb.io.in(3) <> rocc.io.dmem
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ptw.io.requestor(2) <> rocc.io.iptw
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ptw.io.requestor(3) <> rocc.io.dptw
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ptw.io.requestor(4) <> rocc.io.pptw
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}
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}
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