386 lines
15 KiB
Scala
386 lines
15 KiB
Scala
package uncore
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import Chisel._
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import junctions._
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import scala.collection.mutable.ArraySeq
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import cde.{Parameters, Field}
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/** PortedTileLinkNetworks combine a TileLink protocol with a particular physical
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* network implementation.
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*
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* Specifically, they provide mappings between ClientTileLinkIO/
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* ManagerTileLinkIO channels and LogicalNetwork ports (i.e. generic
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* TileLinkIO with networking headers). Channels coming into the network have
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* appropriate networking headers appended and outgoing channels have their
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* headers stripped.
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*
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* @constructor base class constructor for Ported TileLink NoC
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* @param addrToManagerId a mapping from a physical address to the network
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* id of a coherence manager
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* @param sharerToClientId a mapping from the id of a particular coherent
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* client (as determined by e.g. the directory) and the network id
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* of that client
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* @param clientDepths the depths of the queue that should be used to buffer
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* each channel on the client side of the network
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* @param managerDepths the depths of the queue that should be used to buffer
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* each channel on the manager side of the network
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*/
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abstract class PortedTileLinkNetwork(
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addrToManagerId: UInt => UInt,
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sharerToClientId: UInt => UInt,
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clientDepths: TileLinkDepths,
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managerDepths: TileLinkDepths)
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(implicit p: Parameters) extends TLModule()(p) {
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val nClients = tlNClients
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val nManagers = tlNManagers
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val io = new Bundle {
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val clients_cached = Vec(tlNCachingClients, new ClientTileLinkIO).flip
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val clients_uncached = Vec(tlNCachelessClients, new ClientUncachedTileLinkIO).flip
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val managers = Vec(nManagers, new ManagerTileLinkIO).flip
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}
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val clients = (io.clients_cached ++ io.clients_uncached).zipWithIndex.map {
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case (io, idx) => {
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val qs = Module(new TileLinkEnqueuer(clientDepths))
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io match {
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case c: ClientTileLinkIO => {
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val port = Module(new ClientTileLinkNetworkPort(idx, addrToManagerId))
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port.io.client <> c
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qs.io.client <> port.io.network
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qs.io.manager
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}
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case u: ClientUncachedTileLinkIO => {
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val port = Module(new ClientUncachedTileLinkNetworkPort(idx, addrToManagerId))
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port.io.client <> u
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qs.io.client <> port.io.network
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qs.io.manager
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}
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}
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}
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}
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val managers = io.managers.zipWithIndex.map {
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case (m, i) => {
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val port = Module(new ManagerTileLinkNetworkPort(i, sharerToClientId))
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val qs = Module(new TileLinkEnqueuer(managerDepths))
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port.io.manager <> m
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port.io.network <> qs.io.manager
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qs.io.client
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}
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}
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}
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/** A simple arbiter for each channel that also deals with header-based routing.
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* Assumes a single manager agent. */
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class PortedTileLinkArbiter(
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sharerToClientId: UInt => UInt = (u: UInt) => u,
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clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0),
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managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0))
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(implicit p: Parameters)
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extends PortedTileLinkNetwork(u => UInt(0), sharerToClientId, clientDepths, managerDepths)(p)
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with TileLinkArbiterLike
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with PassesId {
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val arbN = nClients
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require(nManagers == 1)
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if(arbN > 1) {
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hookupClientSource(clients.map(_.acquire), managers.head.acquire)
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hookupClientSource(clients.map(_.release), managers.head.release)
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hookupFinish(clients.map(_.finish), managers.head.finish)
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hookupManagerSourceWithHeader(clients.map(_.probe), managers.head.probe)
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hookupManagerSourceWithHeader(clients.map(_.grant), managers.head.grant)
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} else {
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managers.head <> clients.head
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}
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}
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/** Provides a separate physical crossbar for each channel. Assumes multiple manager
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* agents. Managers are assigned to higher physical network port ids than
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* clients, and translations between logical network id and physical crossbar
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* port id are done automatically.
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*/
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class PortedTileLinkCrossbar(
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addrToManagerId: UInt => UInt = u => UInt(0),
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sharerToClientId: UInt => UInt = u => u,
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clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0),
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managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0))
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(implicit p: Parameters)
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extends PortedTileLinkNetwork(addrToManagerId, sharerToClientId, clientDepths, managerDepths)(p) {
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val n = p(LNEndpoints)
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val phyHdrWidth = log2Up(n)
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val count = tlDataBeats
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// Actually instantiate the particular networks required for TileLink
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val acqNet = Module(new BasicBus(CrossbarConfig(n, new Acquire, count, Some((a: PhysicalNetworkIO[Acquire]) => a.payload.hasMultibeatData()))))
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val relNet = Module(new BasicBus(CrossbarConfig(n, new Release, count, Some((r: PhysicalNetworkIO[Release]) => r.payload.hasMultibeatData()))))
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val prbNet = Module(new BasicBus(CrossbarConfig(n, new Probe)))
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val gntNet = Module(new BasicBus(CrossbarConfig(n, new Grant, count, Some((g: PhysicalNetworkIO[Grant]) => g.payload.hasMultibeatData()))))
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val ackNet = Module(new BasicBus(CrossbarConfig(n, new Finish)))
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// Aliases for the various network IO bundle types
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type PNIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]]
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type LNIO[T <: Data] = DecoupledIO[LogicalNetworkIO[T]]
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type FromCrossbar[T <: Data] = PNIO[T] => LNIO[T]
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type ToCrossbar[T <: Data] = LNIO[T] => PNIO[T]
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// Shims for converting between logical network IOs and physical network IOs
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def crossbarToManagerShim[T <: Data](in: PNIO[T]): LNIO[T] = {
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val out = DefaultFromPhysicalShim(in)
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out.bits.header.src := in.bits.header.src - UInt(nManagers)
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out
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}
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def crossbarToClientShim[T <: Data](in: PNIO[T]): LNIO[T] = {
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val out = DefaultFromPhysicalShim(in)
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out.bits.header.dst := in.bits.header.dst - UInt(nManagers)
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out
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}
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def managerToCrossbarShim[T <: Data](in: LNIO[T]): PNIO[T] = {
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val out = DefaultToPhysicalShim(n, in)
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out.bits.header.dst := in.bits.header.dst + UInt(nManagers, phyHdrWidth)
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out
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}
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def clientToCrossbarShim[T <: Data](in: LNIO[T]): PNIO[T] = {
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val out = DefaultToPhysicalShim(n, in)
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out.bits.header.src := in.bits.header.src + UInt(nManagers, phyHdrWidth)
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out
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}
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// Make an individual connection between virtual and physical ports using
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// a particular shim. Also pin the unused Decoupled control signal low.
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def doDecoupledInputHookup[T <: Data](phys_in: PNIO[T], phys_out: PNIO[T], log_io: LNIO[T], shim: ToCrossbar[T]) = {
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val s = shim(log_io)
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phys_in.valid := s.valid
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phys_in.bits := s.bits
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s.ready := phys_in.ready
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phys_out.ready := Bool(false)
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}
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def doDecoupledOutputHookup[T <: Data](phys_in: PNIO[T], phys_out: PNIO[T], log_io: LNIO[T], shim: FromCrossbar[T]) = {
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val s = shim(phys_out)
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log_io.valid := s.valid
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log_io.bits := s.bits
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s.ready := log_io.ready
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phys_in.valid := Bool(false)
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}
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//Hookup all instances of a particular subbundle of TileLink
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def doDecoupledHookups[T <: Data](physIO: BasicCrossbarIO[T], getLogIO: TileLinkIO => LNIO[T]) = {
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physIO.in.head.bits.payload match {
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case c: ClientToManagerChannel => {
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managers.zipWithIndex.map { case (i, id) =>
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doDecoupledOutputHookup(physIO.in(id), physIO.out(id), getLogIO(i), crossbarToManagerShim[T])
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}
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clients.zipWithIndex.map { case (i, id) =>
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doDecoupledInputHookup(physIO.in(id+nManagers), physIO.out(id+nManagers), getLogIO(i), clientToCrossbarShim[T])
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}
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}
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case m: ManagerToClientChannel => {
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managers.zipWithIndex.map { case (i, id) =>
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doDecoupledInputHookup(physIO.in(id), physIO.out(id), getLogIO(i), managerToCrossbarShim[T])
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}
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clients.zipWithIndex.map { case (i, id) =>
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doDecoupledOutputHookup(physIO.in(id+nManagers), physIO.out(id+nManagers), getLogIO(i), crossbarToClientShim[T])
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}
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}
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}
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}
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doDecoupledHookups(acqNet.io, (tl: TileLinkIO) => tl.acquire)
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doDecoupledHookups(relNet.io, (tl: TileLinkIO) => tl.release)
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doDecoupledHookups(prbNet.io, (tl: TileLinkIO) => tl.probe)
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doDecoupledHookups(gntNet.io, (tl: TileLinkIO) => tl.grant)
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doDecoupledHookups(ackNet.io, (tl: TileLinkIO) => tl.finish)
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}
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class ClientUncachedTileLinkIORouter(
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nOuter: Int, routeSel: UInt => UInt)(implicit p: Parameters)
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extends TLModule {
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val io = new Bundle {
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val in = (new ClientUncachedTileLinkIO).flip
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val out = Vec(nOuter, new ClientUncachedTileLinkIO)
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}
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val acq_route = routeSel(io.in.acquire.bits.full_addr())
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io.in.acquire.ready := Bool(false)
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io.out.zipWithIndex.foreach { case (out, i) =>
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out.acquire.valid := io.in.acquire.valid && acq_route(i)
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out.acquire.bits := io.in.acquire.bits
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when (acq_route(i)) { io.in.acquire.ready := out.acquire.ready }
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}
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val gnt_arb = Module(new LockingRRArbiter(
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new Grant, nOuter, tlDataBeats, Some((gnt: Grant) => gnt.hasMultibeatData())))
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gnt_arb.io.in <> io.out.map(_.grant)
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io.in.grant <> gnt_arb.io.out
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assert(!io.in.acquire.valid || acq_route.orR, "No valid route")
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}
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class TileLinkInterconnectIO(val nInner: Int, val nOuter: Int)
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(implicit p: Parameters) extends Bundle {
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val in = Vec(nInner, new ClientUncachedTileLinkIO).flip
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val out = Vec(nOuter, new ClientUncachedTileLinkIO)
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}
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class ClientUncachedTileLinkIOCrossbar(
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nInner: Int, nOuter: Int, routeSel: UInt => UInt)
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(implicit p: Parameters) extends TLModule {
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val io = new TileLinkInterconnectIO(nInner, nOuter)
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if (nInner == 1) {
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val router = Module(new ClientUncachedTileLinkIORouter(nOuter, routeSel))
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router.io.in <> io.in.head
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io.out <> router.io.out
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} else {
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val routers = List.fill(nInner) {
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Module(new ClientUncachedTileLinkIORouter(nOuter, routeSel)) }
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val arbiters = List.fill(nOuter) {
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Module(new ClientUncachedTileLinkIOArbiter(nInner)) }
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for (i <- 0 until nInner) {
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routers(i).io.in <> io.in(i)
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}
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for (i <- 0 until nOuter) {
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arbiters(i).io.in <> routers.map(r => r.io.out(i))
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io.out(i) <> arbiters(i).io.out
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}
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}
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}
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abstract class TileLinkInterconnect(implicit p: Parameters) extends TLModule()(p) {
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val nInner: Int
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val nOuter: Int
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lazy val io = new TileLinkInterconnectIO(nInner, nOuter)
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}
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class TileLinkRecursiveInterconnect(val nInner: Int, addrMap: AddrMap)
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(implicit p: Parameters) extends TileLinkInterconnect()(p) {
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def port(name: String) = io.out(addrMap.port(name))
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val nOuter = addrMap.numSlaves
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val routeSel = (addr: UInt) =>
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Cat(addrMap.entries.map(e => addrMap(e.name).containsAddress(addr)).reverse)
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val xbar = Module(new ClientUncachedTileLinkIOCrossbar(nInner, addrMap.length, routeSel))
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xbar.io.in <> io.in
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io.out <> addrMap.entries.zip(xbar.io.out).flatMap {
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case (entry, xbarOut) => {
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entry.region match {
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case submap: AddrMap if submap.isEmpty =>
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xbarOut.acquire.ready := Bool(false)
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xbarOut.grant.valid := Bool(false)
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None
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case submap: AddrMap =>
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val ic = Module(new TileLinkRecursiveInterconnect(1, submap))
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ic.io.in.head <> xbarOut
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ic.io.out
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case _ =>
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Some(xbarOut)
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}
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}
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}
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}
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class TileLinkMemoryInterconnect(
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nBanksPerChannel: Int, nChannels: Int)
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(implicit p: Parameters) extends TileLinkInterconnect()(p) {
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val nBanks = nBanksPerChannel * nChannels
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val nInner = nBanks
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val nOuter = nChannels
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def connectChannel(outer: ClientUncachedTileLinkIO, inner: ClientUncachedTileLinkIO) {
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outer <> inner
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outer.acquire.bits.addr_block := inner.acquire.bits.addr_block >> UInt(log2Ceil(nChannels))
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}
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for (i <- 0 until nChannels) {
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/* Bank assignments to channels are strided so that consecutive banks
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* map to different channels. That way, consecutive cache lines also
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* map to different channels */
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val banks = (i until nBanks by nChannels).map(j => io.in(j))
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val channelArb = Module(new ClientUncachedTileLinkIOArbiter(nBanksPerChannel))
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channelArb.io.in <> banks
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connectChannel(io.out(i), channelArb.io.out)
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}
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}
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/** Allows users to switch between various memory configurations. Note that
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* this is a dangerous operation: not only does switching the select input to
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* this module violate TileLink, it also causes the memory of the machine to
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* become garbled. It's expected that select only changes at boot time, as
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* part of the memory controller configuration. */
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class TileLinkMemorySelectorIO(val nBanks: Int, val maxMemChannels: Int, nConfigs: Int)
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(implicit p: Parameters)
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extends TileLinkInterconnectIO(nBanks, maxMemChannels) {
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val select = UInt(INPUT, width = log2Up(nConfigs))
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override def cloneType =
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new TileLinkMemorySelectorIO(nBanks, maxMemChannels, nConfigs).asInstanceOf[this.type]
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}
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class TileLinkMemorySelector(nBanks: Int, maxMemChannels: Int, configs: Seq[Int])
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(implicit p: Parameters)
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extends TileLinkInterconnect()(p) {
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val nInner = nBanks
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val nOuter = maxMemChannels
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val nConfigs = configs.size
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override lazy val io = new TileLinkMemorySelectorIO(nBanks, maxMemChannels, nConfigs)
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def muxOnSelect[T <: Data](up: DecoupledIO[T], dn: DecoupledIO[T], active: Bool): Unit = {
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when (active) { dn.bits := up.bits }
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when (active) { up.ready := dn.ready }
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when (active) { dn.valid := up.valid }
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}
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def muxOnSelect(up: ClientUncachedTileLinkIO, dn: ClientUncachedTileLinkIO, active: Bool): Unit = {
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muxOnSelect(up.acquire, dn.acquire, active)
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muxOnSelect(dn.grant, up.grant, active)
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}
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def muxOnSelect(up: Vec[ClientUncachedTileLinkIO], dn: Vec[ClientUncachedTileLinkIO], active: Bool) : Unit = {
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for (i <- 0 until up.size)
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muxOnSelect(up(i), dn(i), active)
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}
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/* Disconnects a vector of TileLink ports, which involves setting them to
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* invalid. Due to Chisel reasons, we need to also set the bits to 0 (since
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* there can't be any unconnected inputs). */
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def disconnectOuter(outer: Vec[ClientUncachedTileLinkIO]) = {
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outer.foreach{ m =>
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m.acquire.valid := Bool(false)
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m.acquire.bits := m.acquire.bits.fromBits(UInt(0))
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m.grant.ready := Bool(false)
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}
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}
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def disconnectInner(inner: Vec[ClientUncachedTileLinkIO]) = {
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inner.foreach { m =>
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m.grant.valid := Bool(false)
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m.grant.bits := m.grant.bits.fromBits(UInt(0))
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m.acquire.ready := Bool(false)
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}
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}
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/* Provides default wires on all our outputs. */
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disconnectOuter(io.out)
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disconnectInner(io.in)
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/* Constructs interconnects for each of the layouts suggested by the
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* configuration and switches between them based on the select input. */
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configs.zipWithIndex.foreach{ case (nChannels, select) =>
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val nBanksPerChannel = nBanks / nChannels
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val ic = Module(new TileLinkMemoryInterconnect(nBanksPerChannel, nChannels))
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disconnectInner(ic.io.out)
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disconnectOuter(ic.io.in)
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muxOnSelect(io.in, ic.io.in, io.select === UInt(select))
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muxOnSelect(ic.io.out, io.out, io.select === UInt(select))
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}
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}
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