Christopher Celio e22bf02a80 [commitlog] CSR's cycle optionally set to instret ...

- Allows debugging Rocket against Spike by having timer interrupts
    occur in the same place in the instruction stream for both.

2015-09-15 16:47:26 -07:00

..

main/scala

[commitlog] CSR's cycle optionally set to instret

2015-09-15 16:47:26 -07:00