Andrew Waterman e140893a01 Use 1-entry queue on processor-side E-channel ... The cache can't sink a grant every cycle, so extra E buffering doesn't help.		2017-07-31 18:06:54 -07:00
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amba	tilelink: Error device supports Acquire	2017-07-27 18:32:58 -07:00
config	Refactor package hierarchy and remove legacy bus protocol implementations (#845)	2017-07-07 10:48:16 -07:00
coreplex	systembus: all slaves should have an output buffer	2017-07-29 00:13:33 -07:00
devices	TLError: does not need to be fast; cut the loop	2017-07-29 00:22:21 -07:00
diplomacy	Merge pull request #900 from freechipsproject/more_verbose_requires	2017-07-28 13:23:33 -07:00
groundtest	chiplink: adjust bus view to include the splitter (#886)	2017-07-24 21:41:17 -07:00
jtag	Use chisel3 Clock() method.	2017-07-07 14:16:39 -07:00
regmapper	add cloneType to RegisterWriteIO and RegisterReadIO (#874)	2017-07-18 18:52:31 -07:00
rocket	Fix a D$ ready-valid signaling regression	2017-07-31 18:05:14 -07:00
system	tilelink: Error device supports Acquire	2017-07-27 18:32:58 -07:00
tile	Use 1-entry queue on processor-side E-channel	2017-07-31 18:06:54 -07:00
tilelink	tilelink: use the Monitor to enforce Probe sourcing	2017-07-28 18:08:00 -07:00
unittest	Combine Coreplex and System Module Hierarchies (#875)	2017-07-23 08:31:04 -07:00
util	util: tweak rational crossings to avoid mux in source	2017-07-31 15:10:15 -07:00